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参数资料
| 型号： | ACS8946 |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC48 |
| 封装： | 7 X 7 MM, QFN-48 |
| 文件页数： | 6/40页 |
| 文件大小： | 663K |
| 代理商： | ACS8946 |
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 14
www.semtech.com
ACS8946 JAM PLL
Define/change the frequencies of the dynamically
controllable outputs OUT1/OUT2 by driving the
RATE[2:1]A/B pins high or low in accordance with the
AB pattern for the required frequency as given in
Using CFG_IN[3:2], select the output interface type
(CML/LVPECL) for outputs OUT1 and OUT2. (See
Using CFG_IN[7:6], enable/disable LOCKB, select the
required output interface type for OUT3/OUT4 and set
any odd division. If odd division is not required, set to
1. (See Table 13).
Example Configuration
Decide which set of four output rates is most appropriate
for the application and look for the configuration that
provides these “Available Rates” in Table 11. E.g. If
77.76 MHz, 38.88 MHz, 19.44 MHz and 0ff are required,
then configuration No. 34 in Table 11 will suffice, i.e.
connect CFG_IN0 to ALARMC_CO3 and connect CFG_IN1
to CFG_OUT2.
To set OUT3 or OUT4 requires the additional configuration
of CFG_IN4 and CFG_IN5 as given by Table 12 (which also
configures RESYNC Edge). If OUT4 is required to be set to
“Off”, since “Off” has already been defined by previous
selection as AB=00 in Table 11, then look up the 00
pattern in Table 12, under “resulting RATE 4[AB]” (giving
rows 0 to3 and 16 to 19). Now refine the selection such
that OUT 3 provides 19.44 MHz output (AB=01) and a
rising RESYNC edge is required - this points to row 17 only,
i.e. connect CFG_IN4 to ALARM1_CO0 and connect
CFG_IN5 to ALARMC-CO3.
Set each of OUT[2:1] to one of these four Available Rates,
as required using the rate selection pins, e.g. to set
Output OUT2 to output 38.88 MHz, set RATE2A =1 and
RATE2B=0.
To configure an input to the required frequency of
77.76 MHz (and Output technology for OUT 1 and OUT2
only to CML), configure CFG_IN2 to GND and CFG_IN3 to
CFG_OUT2 as per row 2 in Table 10.
Table 13 provides the configuration information for using
pins CFG_IN[7:6] to configure whether LOCKB is enabled
or disabled, the value of the odd divider, and the port
interface type for OUT3 and OUT4. For example, assuming
LVPECL interface type is required, LOCKB is to be enabled
and the output rates (set previously according to Tables
Rates” of Off, 3.888 MHz,7.776 MHz, 15.552 MHz, then
use the configuration in row 9 of Table 13, i.e. wire
CFG_IN6 to VDD and CFG_IN7 to ALARM2_CO1. The
corresponding frequency selections made for OUT[4:1]
will be divided by 5. The configuration of row 15 would be
used if the odd divider is not required (i.e. set to divide-
by-1).
Table 10 Input Divider, and OUT 1 and OUT2 Output Interface Type Configurations
Row
no.
Wiring of Configuration Pins
Output Application
Required Input
Frequency/
MHz
Resulting Highest
Available Output
Frequency/MHz
(when no further
division is selected)
Output Interface
Type for OUT1 and
OUT2
CFG_IN2
CFG_IN3
0
GND
ALARM1_CO0
SONET/SDH
155.52
622.08
CML
1
GND
ALARM2_CO1
SONET/SDH
155.52
622.08
LVPECL
2
GND
CFG_OUT2
SONET/SDH
77.76
622.08
CML
3
GND
ALARMC_CO3
SONET/SDH
77.76
622.08
LVPECL
4
VDD
GND
SONET/SDH
38.88
622.08
CML
5
VDD
SONET/SDH
38.88
622.08
LVPECL
6
VDD
ALARM1_CO0
SONET/SDH
19.44
622.08
CML
7
VDD
ALARM2_CO1
SONET/SDH
19.44
622.08
LVPECL
CFG_OUT2
ALARM1_CO0
Ethernet
125.00
625.00
CML
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