参数资料
| 型号： | AD2S1210BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/36页 |
| 文件大小： | 0K |
| 描述： | IC CONV R/D 10-16BIT 48-LQFP |
| 标准包装： | 1 |
| 类型： | R/D 转换器 |
| 分辨率（位）： | 10，12，14，16 b |
| 数据接口： | 串行，并联 |
| 电压电源： | 模拟和数字 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 790 (CN2011-ZH PDF) |
| 配用： | EVAL-AD2S1210EDZ-ND - BOARD EVAL AD2S1210 |
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AD2S1210
Rev. A | Page 10 of 36
Pin
No.
Mnemonic
Description
13
DB13/SCLK
Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state data output pin controlled by CS and RD. In
serial mode, this pin acts as the serial clock input.
14 to
17
DB12 to
DB9
Data Bit 12 to Data Bit 9. Three-state data output pins controlled by CS and RD.
18
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Decouple this pin to DGND. The voltage range on this pin is 2.3 V to 5.25 V and may be different to the voltage range
at AVDD and DVDD but should never exceed either by more than 0.3 V.
20
DB8
Data Bit 8. Three-state data output pin controlled by CS and RD.
21 to
28
DB7 to DB0
Data Bit 7 to Data Bit 0. Three-state data input/output pins controlled by CS, RD, and WR/FSYNC.
29
A
Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
30
B
Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format
input signals applied to the converter are valid.
31
NM
North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the
resolver format input signals applied to the converter are valid.
32
DIR
Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR
output indicates the direction of the input rotation and is high for increasing angular rotation.
33
RESET
Reset. Logic input. The AD2S1210 requires an external reset signal to hold the RESET input low until VDD is within the
specified operating range of 4.75 V to 5.25 V.
34
LOT
Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. Refer to the Loss of
Position Tracking Detection section.
35
DOS
Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine)
exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and
cosine input voltages. DOS is indicated by a logic low on the DOS pin. Refer to the Signal Degradation Detection
section.
36
A1
Mode Select 1. Logic input. A1 in conjunction with A0 allows the mode of the AD2S1210 to be selected. Refer to the
Configuration of AD2S1210 section.
37
A0
Mode Select 0. Logic input. A0 in conjunction with A1 allows the mode of the AD2S1210 to be selected. Refer to the
Configuration of AD2S1210 section.
38
EXC
Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its
complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation
frequency register.
39
EXC
Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal
(EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the
excitation frequency register.
40
AGND
Analog Ground. This pin is the ground reference points for analog circuitry on the AD2S1210. Refer all analog input
signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a
system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
41
SIN
Positive Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
42
SINLO
Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
43
AVDD
Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210. The
AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
44
COSLO
Negative Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
45
COS
Positive Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.
46
REFBYP
Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are 10 μF and 0.01 μF.
47
REFOUT
Voltage Reference Output.
48
RES0
Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the resolution of the AD2S1210 to be
programmed. Refer to the Configuration of AD2S1210 section.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD2S1210BSTZ-DASSAULT | 制造商:Analog Devices 功能描述: |
| AD2S1210CSTZ | 功能描述:IC CONV R/D VAR RES OSC 48-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - ADCs/DAC - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:数据采集系统（DAS） 分辨率（位）:16 b 采样率（每秒）:21.94k 数据接口:MICROWIRE?，QSPI?，串行，SPI? 电压电源:模拟和数字 电源电压:1.8 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（6x6） 包装:托盘 |
| AD2S1210DSTZ | 功能描述:IC CONV R/D VAR RES OSC 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - ADCs/DAC - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:数据采集系统（DAS） 分辨率（位）:16 b 采样率（每秒）:21.94k 数据接口:MICROWIRE?，QSPI?，串行，SPI? 电压电源:模拟和数字 电源电压:1.8 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（6x6） 包装:托盘 |
| AD2S1210DSTZ | 制造商:Analog Devices 功能描述:IC, ADC, 16BIT, PARALLEL, SERIAL, LQFP-4 |
| AD2S1210SST-EP-RL7 | 功能描述:模数转换器 - ADC IC 10-16 Bit R/D Cnvtr w/Ref Oscilltr RoHS:否 制造商:Analog Devices 通道数量: 结构: 转换速率: 分辨率: 输入类型: 信噪比: 接口类型: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
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