参数资料
| 型号： | AD5372BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/29页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 32CH SER 64-LQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 设置时间： | 20µs |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 32 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 520mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 输出数目和类型： | 32 电压，单极；32 电压，双极 |
| 采样率（每秒）： | * |
| 产品目录页面： | 782 (CN2011-ZH PDF) |
| 配用： | EVAL-AD5372EBZ-ND - BOARD EVAL FOR AD5372 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
AD5372/AD5373
Rev. C | Page 15 of 28
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5372/AD5373 contain 32 DAC channels and 32 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit (AD5372) or 14-bit (AD5373)
resistor-string DAC followed by an output buffer amplifier.
The resistor-string section is simply a string of resistors (of
equal value) from VREF0 or VREF1 to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit
(AD5372) or 14-bit (AD5373) binary digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off before being fed into the output amplifier.
The output amplifier multiplies the DAC output voltage by 4.
The nominal output span is 12 V with a 3 V reference and 20 V
with a 5 V reference.
CHANNEL GROUPS
The 32 DAC channels of the AD5372/AD5373 are arranged into
four groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 3 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
Table 7. AD5372/AD5373 Registers
Register Name
Word Length
in Bits
Description
X1A (Group) (Channel)
16 (14)
Input Data Register A, one for each DAC channel.
X1B (Group) (Channel)
16 (14)
Input Data Register B, one for each DAC channel.
M (Group) (Channel)
16 (14)
Gain trim registers, one for each DAC channel.
C (Group) (Channel)
16 (14)
Offset trim registers, one for each DAC channel.
X2A (Group) (Channel)
16 (14)
Output Data Register A, one for each DAC channel. These registers store the final, calibrated
DAC data after gain and offset trimming. They are not readable or directly writable.
X2B (Group) (Channel)
16 (14)
Output Data Register B, one for each DAC channel. These registers store the final, calibrated
DAC data after gain and offset trimming. They are not readable or directly writable.
DAC (Group) (Channel)
Data registers from which the DACs take their final input data. The DAC registers are updated
from the X2A or X2B registers. They are not readable or directly writable.
OFS0
14
Offset DAC 0 data register: sets offset for Group 0.
OFS1
14
Offset DAC 1 data register: sets offset for Group 1 to Group 3.
Control
3
Bit 2 = A/B.
0 = global selection of X1A input data registers.
1 = global selection of X1B input data registers.
Bit 1 = enable thermal shutdown.
0 = disable thermal shutdown.
1 = enable thermal shutdown.
Bit 0 = software power-down.
0 = software power-up.
1 = software power-down.
A/B Select 0
8
Each bit in this register determines whether a DAC in Group 0 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 1
8
Each bit in this register determines whether a DAC in Group 1 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 2
8
Each bit in this register determines whether a DAC in Group 2 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 3
8
Each bit in this register determines whether a DAC in Group 3 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
Table 8. AD5372/AD5373 Input Register Default Values
Register Name
AD5372 Default Value
AD5373 Default Value
X1A, X1B
0x5554
0x1555
M
0xFFFF
0x3FFF
C
0x8000
0x2000
OFS0, OFS1
0x1555
Control
0x00
A/B Select 0 to A/B Select 3
0x00
相关PDF资料 |
PDF描述 |
|---|---|
| LTC1595AIS8#PBF | IC D/A CONV 16BIT MULTPLYNG8SOIC |
| VE-2TJ-MY-F3 | CONVERTER MOD DC/DC 36V 50W |
| VI-B4Z-MU-F4 | CONVERTER MOD DC/DC 2V 80W |
| LTC2757BILX#PBF | IC DAC 18BIT PAR 48LQFP |
| MS3114E22-41SY | CONN RCPT 41POS JAM NUT W/SCKT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5372BSTZ-REEL | 功能描述:IC DAC 16BIT 32CH SER 64-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD5373BCPZ | 功能描述:数模转换器- DAC 32-CH 14-bit Serial bipolar DAC I.C. RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| AD5373BCPZ-RL7 | 功能描述:14 Bit Digital to Analog Converter 32 56-LFCSP-VQ (8x8) 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:上次购买时间 位数:14 数模转换器数:32 建立时间:30μs 输出类型:Voltage - Buffered 差分输出:无 数据接口:SPI，DSP 参考类型:外部 电压 - 电源，模拟:9 V ~ 16.5 V，-4.5 V ~ 16.5 V 电压 - 电源，数字:2.5 V ~ 5.5 V INL/DNL（LSB）:±1（最大），±1（最大） 架构:电阻串 DAC 工作温度:-40°C ~ 85°C 封装/外壳:56-VFQFN 裸露焊盘，CSP 供应商器件封装:56-LFCSP-VQ（8x8） 标准包装:1 |
| AD5373BSTZ | 功能描述:IC DAC 14BIT 32CH SER 64-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD5373BSTZ-REEL | 功能描述:IC DAC 14BIT 32CH SER 64-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
发布紧急采购，3分钟左右您将得到回复。