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参数资料
| 型号： | AD5933YRSZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/40页 |
| 文件大小： | 0K |
| 描述： | NETWORK ANALYZER 12B 1MSP 16SSOP |
| 产品培训模块： | AD5933 Impedance to Digital Converter Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 500 |
| 分辨率（位）： | 12 b |
| 主 fclk： | 16.776MHz |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-AD5933EBZ-ND - BOARD EVALUATION FOR AD5933 |
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Data Sheet
AD5933
Rev. E | Page 31 of 40
The key point is that the output impedance of the external
has a far less significant effect on gain factor calibration and
subsequent impedance readings in comparison to connecting
the small impedance directly to the VOUT pin (and directly in
series with ROUT). The external amplifier buffers the unknown
impedance from the effects of ROUT and introduces a smaller
output impedance in series with ZUNKNOWN.
For example, if the user measures ZUNKNOWN that is known to
have a small impedance value within the range of 90 Ω to
110 Ω over the frequency range of 30 kHz to 32 kHz, the
user may not be in a position to measure ROUT directly in
the factory/lab. Therefore, the user may choose to add on
an extra amplifier circuit like that shown in Figure 35 to the
signal path of the AD5933. The user must ensure that the
chosen external amplifier has a sufficiently low output series
resistance over the bandwidth of interest in comparison to the
impedance range under test (for an op amp selection guide, see
www.analog.com/opamps). Most amplifiers from Analog
Devices have a curve of closed loop output impedance vs.
frequency at different amplifier gains to determine the output
series impedance at the frequency of interest.
The system settings are
VDD = 3.3 V
VOUT = 2 V p-p
R2 = 20 kΩ
R1 = 4 kΩ
Gain setting resistor = 500
ZUNKNOWN = 100
PGA setting = ×1
To attenuate the excitation voltage at VOUT, choose a ratio
of R1/R2. With the values of R1 = 4 kΩ and R2 = 20 kΩ,
attenuate the signal by 1/5th of 2 V p-p = 400 mV. The
maximum current flowing through the impedance is 400 mV/
90 Ω = 4.4 mA.
The system is subsequently calibrated using the usual method
with a midpoint impedance value of 100 Ω, a calibration
resistor, and a feedback resistor at a midfrequency point in the
sweep. The dynamic range of the input signal to the receive side
of the AD5933 can be improved by increasing the value of the
I-V gain resistor at the RFB pin. For example, increasing the I-V
gain setting resistor at the RFB pin increases the peak-to-peak
signal presented to the ADC input from 400 mV (RFB = 100 Ω)
to 2 V p-p (RFB = 500 Ω).
The gain factor calculated is for a 100 Ω resistor connected
between VOUT and VIN, assuming the output series resistance
of the external amplifier is small enough to be ignored.
When biasing the circuit shown in Figure 35, note that the
receive side of the AD5933 is hard-biased about VDD/2 by
design. Therefore, to prevent the output of the external
amplifier (attenuated AD5933 Range 1 excitation signal) from
saturating the receive side amplifiers of the AD5933, a voltage
equal to VDD/2 must be applied to the noninverting terminal
of the external amplifier.
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