- 您现在的位置：买卖IC网 > PDF目录373890 > AD6620AS (ANALOG DEVICES INC) 65 MSPS Digital Receive Signal Processor PDF资料下载
参数资料
| 型号： | AD6620AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 65 MSPS Digital Receive Signal Processor |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 18/43页 |
| 文件大小： | 354K |
| 代理商： | AD6620AS |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页
AD6620
–18–
REV. 0
CLK
LOGIC "1"
SOFT RESET
CLR
Q
Q
D
ENB
Q
D
IN[15:0]
EXP[2:0]
Q
D
A/B
CLK
REGISTER
Q
D
Q
D
REGISTER
CLK
MULTIPLEXER
D
S
1
S
2
C
CLR
Q
D
SET
Q
DUAL CHANNEL REAL
SINGLE CHANNEL COMPLEX
INT IN[15:0]
INT EXP[2:0]
INT DATA STROBE
CLR
DELAY 7
ENB
Figure 32. Simplified Input Data Port Schematic for the AD6620
Simplified Input Data Port Schematic
Figure 32 details a simplified schematic for the input data port.
The first thing to note is that IN[15:0], EXP[2:0] and A/B are
all synchronously latched with CLK. Note also that upon soft
reset, a seven pipeline delay (sample clock delay) exists in the
data path. This delay is synchronous with CLK, but is in fact
seven valid sample data delays. For instance, in single channel
real mode with full rate timing the delay is seven CLKs. If in-
stead the data rate is one-fourth CLK, then 28 CLKs (i.e.,
seven sample data delays, gated via A/B) occur before valid data
is passed to the NCO stage.
Interfacing AD6620 Inputs to +5 V Logic Gates
None of the inputs to the AD6620 are tolerant of +5 V logic
signals. When interfacing 5 V devices to this product, an interface
gate such as the 74LCX2244 is recommended. If latching must
be performed, 74LCX574 latches may be used. This gate runs
from the +3.3 V supply and is tolerant of +5 V inputs.
OUTPUT DATA PORT
Parallel Output Data Port
The AD6620 provides a choice of two output ports: a 16-bit
parallel port and a synchronous serial port. Output operation
using the serial port is discussed in the next section. The parallel
port is limited to 16 bits. Because pins are shared between the
parallel and serial output ports, only one output mode can be
used. The output mode must be set with a hard reset generated
by at least a 30 ns low time on the
RESET
pin. If the PAR/SER
line is high (Logic “1”), then parallel output data is activated.
The PAR/SER pin should remain static after the output mode
has been set (i.e., PAR/SER should only change when
RESET
is
low).
Data out of the AD6620 is twos complement.
A scale factor is associated with the output port, which allows
the signal level to be adjusted. This scale factor is mapped to
location 309h, Bits 2–0 in the AD6620 internal address space.
This scalar controls the weight of the 16-bit data going to the
parallel port. The scale factor is discussed in the RAM Coeffi-
cient Filter (RCF) section.
The Parallel Mode provides a 16-bit output port, which consti-
tutes the I and Q data for either one or both channels. This port
can run at a maximum of 65 MHz (32.5 MHz I, 32.5 MHz Q).
This rate assumes that there is a minimum decimation of 2 in
the first filter stage (CIC2) or a 2
×
or greater CLK is used. This
decimation is required because for every input word there is
both an I and a Q output. When the data rate and clock rate are
the same (Full Rate Input Timing), the minimum decimation of
2 must occur in CIC2. Refer to CIC2 for more detail.
DV
OUT
DV
OUT
is provided to signal that valid data is present. If this
pin is high, there is a valid data word on the bus. DV
OUT
re-
mains high for two speed clock cycles in Single Channel Real
and Single Channel Complex Mode and for four clock cycles in
Diversity Channel Real mode. After DV
OUT
returns low the Q
data will remain until the next data sample.
I/Q
OUT
When this pin is high the data word represents I data; when
I/Q
OUT
is low Q data is present. This signal will also be low
when DV
OUT
is low since the last word of every data phase is Q
data.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6620S | 65 MSPS Digital Receive Signal Processor |
| AD6620 | 65 MSPS Digital Receive Signal Processor(采样速率65MSPS的数字接收信号处理器) |
| AD6622AS | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620AS-REEL | 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP T/R |
| AD6620ASZ | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
发布紧急采购，3分钟左右您将得到回复。