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参数资料
| 型号： | AD6620AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 65 MSPS Digital Receive Signal Processor |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 37/43页 |
| 文件大小： | 354K |
| 代理商： | AD6620AS |
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AD6620
–37–
REV. 0
The AD6620 supports four op codes as shown below. These
instructions set the mode of the JTAG interface.
Table XVI.
Instruction
Op Code
IDCODE
BYPASS
SAMPLE/PRELOAD
EXTEST
01
11
10
00
The Vendor Identification Code can be accessed through the
IDCODE instruction and has the following format.
Table XVII.
MSB
Version Part Number
LSB
Mandatory
Manufacturing ID #
0000
0010 0111 0111 1110
000 1110 0101
1
A BSDL file for this device is available from Analog Devices,
Inc. Contact Analog Devices, Inc. for more information.
APPLICATIONS
EVALUATION BOARD
An evaluation board is available for the AD6620. This evalua-
tion board comes complete with an AD6620 and interfaces to a
PC through the printer port. The evaluation board comes com-
plete with software to drive the evaluation board and to design
optimized filters for use with the AD6620. The evaluation board
includes a high speed data interface that mates directly with
evaluation boards for high performance converters such as the
AD6600 and AD6640, allowing digital receivers to be bread-
boarded with only an external RF/IF converter and an interface
to the DSP.
The control software allows access to all of the internal registers
to provide complete programming of the device in a lab setting.
The software can process high speed data as well as digitally
filtered data from the AD6620 allowing analysis of both pre and
post filter channel characteristics. The controlling software can
also be used to spectrally sweep the filter performance, greatly
simplifying verification of any given filter design.
AD6620
LATCH
HI SPEED
DATA
HEADER
LATCH
FIFO
LATCH
TRANSCEIVER
PC PRINTER PORT
LATCH
Figure 52. Evaluation Board Block Diagram
As shown in the block diagram below, the high speed data into
the evaluation board is sent to both the AD6620 and the by-pass
latches. On the output of the AD6620, data is available in either
serial or parallel mode. In serial mode, data may be sent directly
to a DSP for system bread-boarding. In parallel mode, the data
may be sent to the on-board FIFO for spectral analysis by the
included software. For additional information, refer to the
evaluation board manual.
FILTER DESIGN
The AD6620 implements a pair of cascaded CIC filters with a
sum of products FIR filter. The frequency characteristics of the
CIC filters have already been documented. Additional reading
on this class of filters can be found in “An Economical Class of
Digital Filters for Decimation and Interpolation,” by Eugene B.
Hogenauer, IEEE Transactions on Acoustics, Speech, and
Signal Processing, Volume ASSP-29, Number 2, April 1981.
The characteristics of the FIR filter are fully programmable.
The coefficients of this filter may be generated in any number
of ways, using standard procedures such as Parks-McClellan.
Available software from Analog Devices that assists in the design
of filters for this product. This software allows comparison be-
tween different distributions of decimation. The software works
independently of the evaluation board, but easily allows transfer
of design data directly to the evaluation board for immediate
verification of the designed filter.
The normal procedure for designing a filter for the chip is as
shown in the flow chart. First, the desired characteristics must
be determined based on the receive channel requirements. The
decimation rates for the CIC filters must then be selected such
that their performance is near that of the desired channel re-
quirements. Finally, an algorithm such as the Parks-McClellan
or Remez exchange is used to compute the final spectral re-
quirements, including droop correction for passband loss of the
CIC filters. If the designed filter meets the requirements, then
the filter is acceptable. If not, another combination of CIC filter
decimation must be examined. Tables III and IV greatly sim-
plify distribution and selection of CIC requirements. The
filter software available from Analog Devices helps to auto-
mate this procedure.
SELECT FILTER
REJECTION
REQUIREMENTS
DOES CIC2 FILTER
PROTECT ENOUGH
BANDWIDTH
SELECT
DECIMATION
RATE FOR CIC5
DESIGN RCF
WITH REMEZ
EXCHANGE
NO
YES
SELECT
DECIMATION
RATE FOR CIC2
DOES CIC5 FILTER
PROTECT ENOUGH
BANDWIDTH
DOES COMPOSITE
FILTER PROVIDE
THE DESIRED
RESULTS
YES
NO
YES
NO
Figure 53. Diagram of Filter Design Software
相关PDF资料 |
PDF描述 |
|---|---|
| AD6620S | 65 MSPS Digital Receive Signal Processor |
| AD6620 | 65 MSPS Digital Receive Signal Processor(采样速率65MSPS的数字接收信号处理器) |
| AD6622AS | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620AS-REEL | 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP T/R |
| AD6620ASZ | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
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