收藏本站
参数资料
型号： AD6620AS
厂商： ANALOG DEVICES INC
元件分类： 微控制器/微处理器
英文描述： 65 MSPS Digital Receive Signal Processor
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP80
封装： PLASTIC, QFP-80
文件页数： 5/43页
文件大小： 354K
代理商： AD6620AS
AD6620
–5–
REV. 0
TIMING CHARACTERISTICS
(C
LOAD
= 40 pF All Outputs)
Test
Level
AD6620AS
Min
Parameter (Conditions)
Temp
Typ
Max
Units
CLK Timing Requirements:
t
CLK
t
CLKL
t
CLKH
Reset Timing Requirements:
t
RESL
Input Data Timing Requirements:
t
SI
Input
1
to CLK Setup Time
t
HI
Input
1
to CLK Hold Time
Parallel Output Switching Characteristics:
t
DPR
CLK to OUT[15:0] Rise Delay
t
DPF
CLK to OUT[15:0] Fall Delay
t
DPR
CLK to DV
OUT
Rise Delay
t
DPF
CLK to DV
OUT
Fall Delay
t
DPR
CLK to I
QOUT
Rise Delay
t
DPF
CLK to I
QOUT
Fall Delay
t
DPR
CLK to A
BOUT
Rise Delay
t
DPF
CLK to A
BOUT
Fall Delay
SYNC Timing Requirements:
t
SY
SYNC
2
to CLK Setup Time
t
HY
SYNC
2
to CLK Hold Time
SYNC Switching Characteristics:
t
DY
CLK to SYNC
3
Delay Time
Serial Input Timing:
t
SSI
SDI to SCLK
t
Setup Time
t
HSI
SDI to SCLK
t
Hold Time
t
HSRF
SDFS to SCLK
u
Hold Time
t
SSF
SDFS to SCLK
t
Setup Time
4
t
HSF
SDFS to SCLK
t
Hold Time
4
Serial Frame Output Timing:
t
DSE
SCLK
u
to SDFE Delay Time
t
SDFEH
SDFE Width High
t
DSO
SCLK
u
to SDO Delay Time
SCLK Switching Characteristics, SBM = “1”
:
t
SCLK
SCLK Period
3
t
SCLKL
SCLK Width Low
t
SCLKH
SCLK Width High
t
SCLKD
CLK to SCLK Delay Time
S
erial Frame Timing
,
SBM = “1”
:
t
DSF
SCLK
u
to SDFS Delay Time
t
SDFSH
SDFS Width High
SCLK Timing Requirements, SBM
=
“0”
:
t
SCLK
SCLK Period
t
SCLKL
SCLK Width Low
t
SCLKH
SCLK Width High
CLK Period
CLK Width Low
CLK Width High
Full
Full
Full
I
IV
IV
15.4
7.0
7.0
ns
ns
ns
0.5
×
t
CLK
0.5
×
t
CLK
RESET
Width Low
Full
I
30.0
ns
Full
Full
IV
IV
–1.0
6.5
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
8.0
7.5
6.5
5.5
7.0
6.0
7.0
5.5
19.5
19.5
19.0
11.5
19.5
13.5
19.5
13.5
ns
ns
ns
ns
ns
ns
ns
ns
Full
Full
IV
IV
–1.0
6.5
ns
ns
Full
V
7.0
23.5
ns
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
1.0
2.0
4.0
1.0
2.0
ns
ns
ns
ns
ns
Full
Full
Full
IV
V
IV
3.5
11.0
ns
ns
ns
t
SCLK
4.5
11.0
Full
Full
Full
Full
I
V
V
V
2
×
t
CLK
ns
ns
ns
ns
0.5
×
t
SCLK
0.5
×
t
SCLK
6.5
13.0
Full
Full
IV
V
1.0
4.0
ns
ns
t
SCLK
Full
Full
Full
I
IV
IV
15.4
0.4
×
t
SCLK
0.4
×
t
SCLK
ns
ns
ns
0.5
×
t
SCLK
0.5
×
t
SCLK
NOTES
1
Specification pertains to: IN[15:0], EXP[2:0], A/B.
2
Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
3
SCLK period will be
≥
2
×
t
CLK
when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
4
SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
Specifications subject to change without notice.
相关PDF资料
PDF描述
AD6620S 65 MSPS Digital Receive Signal Processor
AD6620 65 MSPS Digital Receive Signal Processor(采样速率65MSPS的数字接收信号处理器)
AD6622AS Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
AD6622PCB Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
AD6622S Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
相关代理商/技术参数
参数描述
AD6620AS-REEL 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP T/R
AD6620ASZ 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1
AD6620ASZ-REEL 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1
AD6620PCB 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor
AD6620S 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*