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参数资料
| 型号： | AD6620AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 65 MSPS Digital Receive Signal Processor |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 26/43页 |
| 文件大小： | 354K |
| 代理商： | AD6620AS |
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AD6620
–26–
REV. 0
The maximum number of taps this filter can calculate, N
TAPS
, is
given by the equation below. The value N
TAPS
minus 1 is writ-
ten to the AD6620 internal address space at address 30C hex.
The decimation ratio of this filter, M
RCF
, may be programmed
from 1 to 32. The input rate into the RCF is f
SAMP5
. N
CH
is equal
to two for Diversity Channel Real Input mode; otherwise N
CH
= 1.
N
f
M
f
N
TAPS
CLK
RCF
SAMPS
CH
≤
×
min
,256
The RCF coefficients are located in addresses 0x000 to 0x0FF
and are interpreted as 20-bit twos complement numbers. When
writing the coefficient RAM, the lower addresses will be multi-
plied by relatively older data from the CIC5 and the higher
coefficient addresses will be multiplied by relatively newer data
from the CIC5. The coefficients need not be symmetric and the
coefficient length, N
TAPS
, may be even or odd. If the coefficients
are symmetric, then both sides of the impulse response must be
written into the coefficient RAM.
The RCF stores the data from the CIC5 into a 256
×
36 RAM.
256
×
18 is assigned to I data and 25
×
18 is assigned to Q data.
The RCF uses the RAM as a circular buffer, so that it is difficult
to know in which address a particular data element is stored. To
avoid start-up transients due to undefined data RAM values, the
data RAM should be cleared upon initialization. The RCF
utilizes the number of data RAM locations equal to N
TAPS
×
N
CH
,
rounded up to the nearest even number, starting from address
0x100, so these are the only values that need be cleared.
When the RCF is triggered to calculate a filter output, it starts
by multiplying the oldest value in the data RAM by the first
coefficient (located by the RCF
OFF
register in address 0x30B).
This value is accumulated with the products of newer data words
multiplied by the subsequent locations in the coefficient RAM
until the coefficient address RCF
OFF
+ N
TAPS
–1 is reached.
Table V. Three-Tap Filter
Coefficient Address
Impulse Response
Data
0
1
2 (N
TAPS
– 1)
h(0)
h(1)
h(2)
n(0) Newest
n(1)
n(2) Oldest
The output rate of this filter is determined by the output rate of
the CIC5 stage and MRCF.
f
f
M
SAMPR
SAMP
RCF
=
5
RCF Coefficient Address Offset
This register at address 30C hex allows the AD6620 to place
multiple filters in the RAM. However, the sum of the taps re-
quired may not exceed 256 divided by the number of channels.
The RCF will compute the filter from RCF_OFFSET to
(RCF_OFFSET + N
TAPS
). A single access can then be used to
select which of the filters is used without requiring coefficients
be rewritten.
RCF Output Scale Factor
The scale factor associated with the RCF, S
OUT
, behaves differ-
ently than the scale factors in the CIC stages. This scalar, at the
RCF output, controls the weight of the 16-bit output data going
to the parallel port or to the serial port when using 16-bit words.
S
OUT
determines which of the 23 RCF output bits are used
based on the equation below. OL
RCF
is the 23-bit RCF output
data; POL represents the output port data. POL is rounded to
the 16 bits desired. The weight of the rounding is adjusted by
S
OUT
. When the serial port is used with 24-bit or 32-bit words,
S
OUT
is ignored.
POL
round OL
RCF
(
S
OUT
=
×
,
)
(
–
7
)
2
16
Filter Phase Synchronization
Like the NCO, the AD6620 filter stages have phase synchroni-
zation circuitry enabling multiple AD6620s to be used in appli-
cations such as diversity antennas and phased array systems.
For any f
SAMP
, there are M
CIC2
possible phases of f
SAMP2
at the
output of the CIC2 stage. Similarly, at the output of the CIC5
stage, there are M
CIC5
possible phases of f
SAMP5
. This means that
at the output of the CIC stages there is already M
CIC2
×
M
CIC5
possible phases of the filtered data. Additional phase uncertainty
is introduced by decimation done in the RCF. At the output of
the AD6620 there are a total of M
CIC2
×
M
CIC5
×
M
RCF
possible
output phases of the data.
In diversity systems using multiple AD6620s, it is necessary to
ensure that the output of each AD6620 in the system is in phase.
A variety of system issues (e.g., not bringing the AD6620s on
line at the same time, excessive digital noise) could cause the
AD6620s to start out-of-phase or to drift out-of-phase as the
system runs. To achieve output phase coherence in such sys-
tems the SYNC_CIC and SYNC_RCF pins are provided.
The function of these pins is controlled by the SYNC_M/S bit
in the Mode Control Register at address 300 hex of internal
address space. When the SYNC_M/S bit is high, SYNC_CIC
and SYNC_RCF provide synchronization pulses on the rising
edge of CLK. When the SYNC_M/S bit is low, SYNC_CIC and
SYNC_RCF accept external synchronization pulses sampled on
the rising edge of clock. This pulse edge synchronizes the CIC2,
CIC5 and RCF filter stages of all AD6620 in the chain.
Below is an example of the output SYNC pulse waveforms.
The SYNC_NCO pulse is not shown and is described in the
preceding NCO Synchronization section. Each SYNC_RCF
output pulse is concurrent with a SYNC_CIC pulse. The
SYNC_RCF output pulse can be connected to the SYNC_CIC,
and SYNC_RCF inputs of another AD6620 to achieve full
decimation synchronization.
CLK
SYNC CIC
SYNC RCF
Figure 46. SYNC Output Pulses
In the example above, M
CIC2
= 2, and M
CIC5
= 2 as evidenced
by the SYNC_CIC pulses that occur every 4 CLK cycles
(M
CIC2
×
M
CIC5
). M
RCF
= 3, resulting in SYNC_RCF pulses
that are one third as frequent as the SYNC_CIC pulses. In this
example full rate input timing is employed such that the input
data rate equals the clock rate.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620AS-REEL | 制造商:Analog Devices 功能描述:Signal Processor 80-Pin PQFP T/R |
| AD6620ASZ | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6620PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
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