- 您现在的位置：买卖IC网 > PDF目录373890 > AD6620S (Analog Devices, Inc.) 65 MSPS Digital Receive Signal Processor PDF资料下载
参数资料
| 型号： | AD6620S |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 65 MSPS Digital Receive Signal Processor |
| 中文描述： | 65 MSPS的数字接收信号处理器 |
| 文件页数： | 38/43页 |
| 文件大小： | 354K |
| 代理商： | AD6620S |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页
AD6620
–38–
REV. 0
SERIAL BUFFERING
The AD6620 serial outputs are designed to operate at very high
speed. As such, care must be taken when driving the serial out-
put lines. These high speed lines must be treated as transmis-
sion lines. Critical lines include the SCLK, SDFS, SDFE, SDI
and SDO. It is recommended that these lines be series source
terminated with the characteristic impedance of the driven line.
If the lines are longer than a few inches, digital line buffers
should be used as shown below. Buffering in this manner will
prevent reflections on the serial lines from disrupting operation
of the AD6620. A good reference on transmission lines is found
in the “MECL System Design Handbook” by Motorola Inc,
Stock code HB205R1/D.
AD6620
SCLK
SDO
SDFS
SCLK
SDO
SDFS
Figure 54. Serial Line Buffering and Series Source
Termination
DSP/SHARC
INTERFACING
With little effort, the AD6620 will interface to nearly all indus-
try standard DSPs, as shown in the figure below. The figures
below show operation in TDM applications as well as in serial
slave mode.
In TDM mode the first AD6620 is configured to be the master.
This chip is the first to access the serial data bus. When the
master has data available in its output shifters, it generates an
SDFS telling the DSP that serial data will follow. At this point,
the SDO of the master AD6620 takes control of the SDO line
and begins shifting data out of the device. When all data has
been shifted, the master raises the SDFE on the last shifted.
This signals the next chip (slave) that on the next cycle of the
clock it should take control of the SDO line and begin shifting
data to the DSP. When the second AD6620 completes its shift,
it raises its SDFE to signal the next chip in the chain, if present.
If additional devices are connected to the chain, this would be
used to indicate they should take control on the next clock cycle.
This application does not have a third device and therefore, the
frame would end.
Normally in an application with a single AD6620, the AD6620
would be configured as the serial bus master. However, there
are applications where the DSP or other device may be the serial
bus master. In this case, the diagram below illustrates how to
configure the AD6620 so that it may be used in this mode. In
order to use this in a meaningful application, the DSP must
know when the AD6620 has new data available on its output. If
the DSP polls the AD6620 too early, either old data will be
resent or the data could be in an indeterminate state. To pre-
vent this, the AD6620 has an output pin DV
OUT
that signals the
DSP when new data is available. This should be tied to an inter-
rupt line of the DSP that is edge-sensitive, as the DV
OUT
line is
only valid for two or four high speed clock cycles depending on
the mode of the chip. The DSP may then invoke an interrupt
service routine to handle the data, see text below. In this appli-
cation, the DSP is responsible for generating the framing and
clocking signals to the AD6620 as shown in Figure 56.
SCLK
AD6620
DSP
+3.3V
SBM
SCLK
SDI
DT
SDO
DR
SDFS
RFS
SDFE
10k
V
SDIV
2
4
AD
WL
10k
V
SCLK
AD6620
CASCADE
SBM
SDI
SDO
SDFS
SDFE
SDIV
2
4
AD
WL
Figure 55. Dual AD6620s Using the Serial Bus in a TDM
Application
SCLK
AD6620
DSP
SBM
SCLK
SDI
DT
SDO
DR
SDFS
RFS
SDFE
10k
V
10k
V
SDIV
2
4
AD
WL
DV
OUT
IRQ
Figure 56. AD6620 Configured as a Serial Slave
SHARC is a registered trademark of Analog Devices, Inc.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6620 | 65 MSPS Digital Receive Signal Processor(采样速率65MSPS的数字接收信号处理器) |
| AD6622AS | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622 | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620S/PCB | 制造商:Analog Devices 功能描述:DUAL CHANNEL DECIMATING RECEIV 制造商:Analog Devices 功能描述:SGNL PROCESSOR 169CSPBGA - Bulk |
| AD6622 | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622AS | 制造商:Analog Devices 功能描述:Transmit Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL 65 MSPS DIGITAL UPCONVERTER - Bulk |
| AD6622PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
发布紧急采购，3分钟左右您将得到回复。