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参数资料
| 型号： | AD6657BBCZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Quad IF Receiver; Package: Chip Scale BGA; No of Pins: 144; Temperature Range: Ind |
| 中文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PBGA144 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MO-205AC, CSPBGA-144 |
| 文件页数： | 10/32页 |
| 文件大小： | 1021K |
| 代理商： | AD6657BBCZ |
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AD6657
Rev. A | Page 18 of 32
431nH
VCM
AIN–
ADC
INTERNAL
INPUT Z
ANALOG
INPUT
XFMR 1:4 Z
ETC4-1T-7
INPUT
Z = 50
3.0pF
3.0k
33
121
33
0.1F
08
557
-116
Figure 34. 1:4 Transformer Passive Configuration
AD8376
AD6657
1H
1nF
VPOS
VCM
15pF
68nH
3.0k║3.0pF
301
165
5.1pF 3.9pF
180nH
1000pF
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1H CHOKE INDUCTORS (0603LS).
180nH
220nH
085
57
-115
Figure 35. Active Front-End Configuration Using the AD8376
For the popular IF band of 140 MHz, Figure 34 shows an
example of a 1:4 transformer passive configuration where a
differential inductor is used to resonate with the internal input
capacitance of the AD6657. This configuration realizes excellent
noise and distortion performance. Figure 35 shows an example
of an active front-end configuration using the AD8376 dual
VGA. This configuration is recommended when signal gain
is required.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6657 sample clock inputs,
CLK+ and CLK, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
(see Figure 36) and require no external bias.
1.2V
AVDD
2pF
CLK–
CLK+
08
55
7-
0
55
Figure 36. Equivalent Clock Input Circuit
Clock Input Options
The AD6657 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern (see the Jitter Considerations section).
ing the AD6657 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer config-
uration is recommended for clock frequencies from 10 MHz to
200 MHz. The back-to-back Schottky diodes across the trans-
former/balun secondary limit clock excursions into the AD6657
to approximately 0.8 V p-p differential.
This limit helps to prevent the large voltage swings of the clock
from feeding through to other portions of the AD6657 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
ADT1-1WT, 1:1Z
XFMR
08
55
7-
0
5
6
Figure 37. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
1nF
CLOCK
INPUT
1nF
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
08
55
7-
0
57
Figure 38. Balun-Coupled Differential Clock (Up to 625 MHz)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6657BBCZRL | 功能描述:IC IF RCVR 11BIT 200MSPS 144BGA RoHS:是 类别:RF/IF 和 RFID >> RF 其它 IC 和模块 系列:- 标准包装:100 系列:* |
| AD6657EBZ | 功能描述:BOARD EVALUATION FOR AD6657 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| AD6659 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual IF Receiver |
| AD6659-80EBZ | 功能描述:BOARD EVALUATION FOR AD6659 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| AD6659BCPZ-80 | 功能描述:IC IF TO BASEBAND RCVR 64LFCSP RoHS:是 类别:RF/IF 和 RFID >> RF 其它 IC 和模块 系列:- 标准包装:100 系列:* |
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