- 您现在的位置：买卖IC网 > PDF目录294844 > AD6657BBCZ (ANALOG DEVICES INC) Quad IF Receiver; Package: Chip Scale BGA; No of Pins: 144; Temperature Range: Ind PDF资料下载
参数资料
| 型号： | AD6657BBCZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Quad IF Receiver; Package: Chip Scale BGA; No of Pins: 144; Temperature Range: Ind |
| 中文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PBGA144 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MO-205AC, CSPBGA-144 |
| 文件页数： | 8/32页 |
| 文件大小： | 1021K |
| 代理商： | AD6657BBCZ |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
AD6657
Rev. A | Page 16 of 32
THEORY OF OPERATION
ADC ARCHITECTURE
The AD6657 architecture consists of quad front-end sample-
and-hold circuits, followed by pipelined, switched-capacitor
ADCs. The quantized outputs from each stage are combined
into a final 14-bit result in the digital correction logic. Alter-
nately, the 14-bit result can be processed through the noise
shaping requantizer (NSR) block before it is sent to the digital
correction logic.
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-
ended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjust-
ment of the output drive current. During power-down, the
output buffers go into a high impedance state.
The AD6657 quad IF receiver can simultaneously digitize four
channels, making it ideal for diversity reception and digital pre-
distortion (DPD) observation paths in telecommunication
systems.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD6657 are accomplished
using a 3-wire SPI-compatible serial interface.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6657 is a differential switched-
capacitor circuit that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see Figure 29). When the input is switched
to sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications,
any shunt capacitors should be reduced. In combination with
the driving source impedance, the shunt capacitors limit the
input bandwidth. For more information on this subject, see
Application Note AN-742, Frequency Domain Response of
Switched-Capacitor ADCs; Application Note AN-827, A Resonant
Approach to Interfacing Amplifiers to Switched-Capacitor ADCs;
and the Analog Dialogue article, “Transformer-Coupled Front-End
for Wideband A/D Converters” (see www.analog.com).
CPAR1
CPAR2
S
CFB
CS
BIAS
VIN+
H
VIN–
08
55
7-
03
7
Figure 29. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
the VIN+ and VIN pins should be matched.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD6657 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. An on-board common-mode voltage reference is
included in the design and is available from the VCMx pins.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCMx pin voltage
(typically 0.5 × AVDD). The VCMx pins must be decoupled
to ground by a 0.1 μF capacitor.
相关PDF资料 |
PDF描述 |
|---|---|
| AD7751AN | SPECIALTY ANALOG CIRCUIT, PDIP24 |
| AD7940BRM | 3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| AD7940BRM-REEL7 | 3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| AD7942 | 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN |
| AD7943BN | +3.3 V/+5 V Multiplying 12-Bit DACs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6657BBCZRL | 功能描述:IC IF RCVR 11BIT 200MSPS 144BGA RoHS:是 类别:RF/IF 和 RFID >> RF 其它 IC 和模块 系列:- 标准包装:100 系列:* |
| AD6657EBZ | 功能描述:BOARD EVALUATION FOR AD6657 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| AD6659 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual IF Receiver |
| AD6659-80EBZ | 功能描述:BOARD EVALUATION FOR AD6659 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| AD6659BCPZ-80 | 功能描述:IC IF TO BASEBAND RCVR 64LFCSP RoHS:是 类别:RF/IF 和 RFID >> RF 其它 IC 和模块 系列:- 标准包装:100 系列:* |
发布紧急采购，3分钟左右您将得到回复。