参数资料
| 型号： | AD73311ARSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG FRONT END 20-SSOP |
| 标准包装： | 66 |
| 位数： | 16 |
| 通道数： | 2 |
| 功率（瓦特）： | 50mW |
| 电压 - 电源，模拟： | 3V |
| 电压 - 电源，数字： | 3V |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 799 (CN2011-ZH PDF) |
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AD73311
–22–
REV. B
Control Register A contains a 3-bit field (DC0–2) that is pro-
grammed by the DSP during the programming phase. The default
condition is that the field contains 000b, which is equivalent to
a single device in cascade (see Table XVII). However, for
cascade operation this field must contain a binary value that is
one less than the number of devices in the cascade.
Table XVII. Device Count Settings
DC2
DC1
DC0
Cascade Length
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
PERFORMANCE
As the AD73311 is designed to provide high performance, low
cost conversion, it is important to understand the means by
which this high performance can be achieved in a typical applica-
tion. This section will, by means of spectral graphs, outline the
typical performance of the device and highlight some of the
options available to users in achieving their desired sample
rate, either directly in the device or by doing some post-processing
in the DSP, while also showing the advantages and disadvan-
tages of the different approaches.
Encoder Section
The encoder section samples at DMCLK/256, which gives a
64 kHz output rate for DMCLK equal to 16.384 MHz. The
noise shaping of the sigma-delta modulator also depends on the
frequency at which it is clocked, which means that the best
dynamic performance in a particular bandwidth is achieved by
oversampling at the highest possible rate. If we assume that the
signals of interest are in the voice bandwidth of dc–4 kHz, then
sampling at 64 kHz gives a spectral response which ensures good
SNR performance in the voice bandwidth, as shown in Figure 14.
FREQUENCY – kHz
0
–60
–150
032
5
dB
10
15
20
25
30
–100
S/N+D = 59.4951
Figure 14. FFT (ADC 64 kHz Sampling)
If sampling at 8 kHz is required, the user must implement some
post-processing in the DSP engine to band limit the signal and
decimate the samples to achieve the ultimate sampling rate of
8 kHz. Figure 15 shows the final spectral response of the
64 kHz sampled data having been digitally filtered and deci-
mated to an 8 kHz rate. The filter used was a 6th order ellip-
tical filter.
FREQUENCY – kHz
0
–140
0
4.0
0.5
dB
1.0
1.5
2.0
2.5
3.0
3.5
–20
–60
–80
–100
–120
–40
S/N+D = 80.615918
Figure 15. FFT (ADC 8 kHz Filtered and Decimated from
64 kHz)
The device features an on-chip master clock divider circuit that
allows the sample rate to be reduced. The present choice of
clock divider options permits the device to sample at 64 kHz,
32 kHz, 21.33 kHz, 16 kHz and 12.8 kHz from a 16.384 MHz
master clock. Reducing the DMCLK rate lowers the sampling
rate of the sigma-delta modulator, which causes the noise shaping
to occur in a reduced bandwidth. The SNR performance up to
FS/2 will still be similar to that in the case of 64 kHz sampling,
but will be disimproved in the voice bandwidth due to the re-
duced noise shaping. Figure 16 shows this effect for a sampling
rate of 16 kHz.
FREQUENCY – kHz
0
–140
08
1
dB
234567
–20
–60
–80
–100
–120
–40
S/N+D = 59.162677
Figure 16. FFT (ADC 16 kHz Sampling)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311ARSZ-REEL | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311ARZ | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311ARZ-REEL | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311L | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311LAR | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Bulk |
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