参数资料
| 型号： | AD73311ARSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/36页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG FRONT END 20-SSOP |
| 标准包装： | 66 |
| 位数： | 16 |
| 通道数： | 2 |
| 功率（瓦特）： | 50mW |
| 电压 - 电源，模拟： | 3V |
| 电压 - 电源，数字： | 3V |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 799 (CN2011-ZH PDF) |
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AD73311
–12–
REV. B
FUNCTIONAL DESCRIPTION
Encoder Channel
The encoder channel consists of a switched capacitor PGA and
a sigma-delta analog-to-digital converter (ADC). An on-board
digital filter, which forms part of the sigma-delta ADC, also
performs critical system-level filtering. Due to the high level of
oversampling, the input antialias requirements are reduced such
that a simple single pole RC stage is sufficient to give adequate
attenuation in the band of interest.
Programmable Gain Amplifier
The encoder section’s analog front end comprises a switched
capacitor PGA which also forms part of the sigma-delta modula-
tor. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
Table IV. PGA Settings for the Encoder Channel
IGS2
IGS1
IGS0
Gain (dB)
00
0
00
1
6
01
0
12
01
1
18
10
0
20
10
1
26
11
0
32
11
1
38
ADC
The ADC consists of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bit-stream, representing the analog input
signal, is input to the antialiasing decimation filter. The decimation
filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta Modulator
The AD73311 input channel employs a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as oversampling
where the sampling rate is many times the highest frequency of
interest. In the case of the AD73311, the initial sampling rate of
the sigma-delta modulator is DMCLK/8. The main effect of
oversampling is that the quantization noise is spread over a very
wide bandwidth, up to FS/2 = DMCLK/16 (Figure 6a). This
means that the noise in the band of interest is much reduced.
Another complementary feature of sigma-delta converters is
the use of a technique called noise-shaping. This technique has
the effect of pushing the noise from the band of interest to an
out-of-band position (Figure 6b). The combination of these
techniques, followed by the application of a digital filter, reduces
the noise in band sufficiently to ensure good dynamic perfor-
mance from the part (Figure 6c).
BAND
OF
INTEREST
FS/2
DMCLK/16
BAND
OF
INTEREST
NOISE SHAPING
FS/2
DMCLK/16
BAND
OF
INTEREST
FS/2
DMCLK/16
DIGITAL FILTER
a.
b.
c.
Figure 6. Sigma-Delta Noise Reduction
Figure 7 shows the various stages of filtering that are employed
in a typical AD73311 application. In Figure 7a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes care
of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial over-
sampling rate and the bandwidth of interest. In Figure 7b, the
signal and noise shaping responses of the sigma-delta modulator
are shown. The signal response provides further rejection of any
high frequency signals while the noise shaping will push the
inherent quantization noise to an out-of-band position. The
detail of Figure 7c shows the response of the digital decimation
filter (Sinc-cubed response) with nulls every multiple of DMCLK/
256, which is the decimation filter update rate. The final detail
in Figure 7d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented
according to the user’s requirements and available MIPS. The
filtering in Figures 7a through 7c is implemented in the AD73311.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311ARSZ-REEL | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311ARZ | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311ARZ-REEL | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311L | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311LAR | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Bulk |
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