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参数资料
| 型号： | AD73422BB-80 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer |
| 中文描述： | 24-BIT, 52 MHz, MIXED DSP, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 10/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422BB-80 |
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REV. 0
AD73422
–
10
–
GAIN
1
0/38dB
PGA
DECIMATOR
+6/
–
15dB
PGA
INTER-
POLATOR
V
REF
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
AD73422
AFE SECTION
SDOFS
SDO
AMCLK
SE
ARESET
SCLK2
SDIFS
SDI
ANALOG
SIGMA-DELTA
MODULATOR
GAIN
1
INVERT
SINGLE-ENDED
ENABLE
ANALOG
LOOP-
BACK
REFERENCE
GAIN
1
0/38dB
PGA
DECIMATOR
+6/
–
15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
1-BIT
DAC
DIGITAL
SIGMA-
DELTA
MODULATOR
INTER-
POLATOR
V
REF
VFBN2
VINN2
VINP2
VFBP2
VOUTP2
VOUTN2
ANALOG
SIGMA-DELTA
MODULATOR
SWITCHED
CAPACITOR
LOW-PASS
FILTER
GAIN
1
INVERT
SINGLE-ENDED
ENABLE
ANALOG
LOOP-
BACK
CONTINUOUS
TIME
LOW-PASS
FILTER
1-BIT
DAC
DIGITAL
SIGMA-
DELTA
MODULATOR
SWITCHED
CAPACITOR
LOW-PASS
FILTER
SERIAL
I/O
PORT
Figure 2. Functional Block Diagram of Analog Front End Section
samples at DMCLK/8. Its bitstream output is filtered and deci-
mated by a Sinc-cubed decimator to provide a sample rate se-
lectable from 64 kHz, 32 kHz, 16 kHz or 8 kHz (based on an
AMCLK of 16.384 MHz).
INVERTING
OP AMPS
ANALOG
LOOP-BACK
SELECT
INVERT
CONTINUOUS
TIME
LOW-PASS
FILTER
V
REF
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
AD73422
AFE SECTION
V
REF
ANALOG
GAIN TAP
GAIN
1
+6/
–
15dB
PGA
REFERENCE
SINGLE-ENDED
ENABLE
0/38dB
PGA
Figure 3. Analog Front End Configuration
The DAC channel features a Sinc-cubed interpolator which
increases the sample rate from the selected rate to the digital
sigma-delta modulator rate of DMCLK/8. The digital sigma-
delta modulator’s output bitstream is fed to a single-bit DAC
whose output is reconstructed/filtered by two stages of low-pass
filtering (switched capacitor and continuous time) before being
applied to the differential output driver.
Each channel also features two programmable gain elements,
Analog Gain Tap (AGT) and Digital Gain Tap (DGT), which,
when enabled, add a signed and scaled amount of the input
signal to the DAC’s output signal. This is of particular use in
line impedance balancing when interfacing the AFE to Sub-
scriber Line Interface Circuits (SLICs).
FUNCTIONAL DESCRIPTION - AFE
Encoder Channels
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input anti-
alias requirements are reduced such that a simple single-pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA which also forms part of the sigma-delta modu-
lator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table I, may be
used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
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PDF描述 |
|---|---|
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| AD73422BBZ-40 | 制造商:Analog Devices 功能描述:AUD CODEC 2ADC / 2DAC 16BIT 119BGA - Bulk |
| AD7342AST-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Analog Devices 功能描述: |
| AD7343AST-REEL | 制造商:Analog Devices 功能描述: |
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| AD7344ASTZ | 制造商:Analog Devices 功能描述: |
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