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参数资料
| 型号： | AD73422BB-80 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer |
| 中文描述： | 24-BIT, 52 MHz, MIXED DSP, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 17/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422BB-80 |
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REV. 0
AD73422
–
17
–
Table XIII. Control Register C Description
C
R
E
T
S
I
G
E
R
L
O
R
T
N
O
C
7
6
5
4
3
2
1
0
N
E
V
5
U
R
F
E
R
U
P
C
A
D
U
P
C
D
A
U
P
A
I
U
P
T
G
A
U
P
U
P
Bit
Name
Description
0
1
2
3
4
5
6
7
PU
PUAGT
PUIA
PUADC
PUDAC
PUREF
RU
—
Power-Up Device (0 = Power-Down; 1 = Power-On)
Analog Gain Tap Power (0 = Power-Down; 1 = Power-On)
Input Amplifier Power (0 = Power-Down; 1 = Power-On)
ADC Power (0 = Power-Down; 1 = Power-On)
DAC Power (0 = Power-Down; 1 = Power-On)
REF Power (0 = Power-Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Reserved (Must be Programmed to 0)
Table XIV. Control Register D Description
D
R
E
T
S
I
G
E
R
L
O
R
T
N
O
C
7
6
5
4
3
2
1
0
E
T
U
M
2
S
G
O
1
S
G
O
0
S
G
O
D
O
M
R
2
S
G
I
1
S
G
I
0
S
G
I
Bit
Name
Description
0
1
2
3
4
5
6
7
IGS0
IGS1
IGS2
RMOD
OGS0
OGS1
OGS2
MUTE
Input Gain Select (Bit 0)
Input Gain Select (Bit 1)
Input Gain Select (Bit 2)
Reset ADC Modulator (0 = Off; 1 = Reset Enabled)
Output Gain Select (Bit 0)
Output Gain Select (Bit 1)
Output Gain Select (Bit 2)
Output Mute (0 = Mute Off; 1 = Mute Enabled)
Table XV. Control Register E Description
E
R
E
T
S
I
G
E
R
L
O
R
T
N
O
C
7
6
5
4
3
2
1
0
E
M
T
E
T
G
D
P
Y
B
I
4
A
D
3
A
D
2
A
D
1
A
D
0
A
D
Bit
Name
Description
0
1
2
3
4
5
DA0
DA1
DA2
DA3
DA4
IBYP
DAC Advance Setting (Bit 0)
DAC Advance Setting (Bit 1)
DAC Advance Setting (Bit 2)
DAC Advance Setting (Bit 3)
DAC Advance Setting (Bit 4)
Interpolator Bypass (0 = Bypass Disabled;
1 = Bypass Enabled)
Digital Gain Tap Enable (0 = Disabled; 1 = Enabled)
Test Mode Enable (0 = Disabled; 1 = Enabled)
6
7
DGTE
TME
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