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参数资料
| 型号： | AD73422BB-80 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Dual Low Power CMOS Analog Front End with DSP Microcomputer |
| 中文描述： | 24-BIT, 52 MHz, MIXED DSP, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 27/36页 |
| 文件大小： | 396K |
| 代理商： | AD73422BB-80 |
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AD73422
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27
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MEMORY ARCHITECTURE
The AD73422 provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory and I/O. Refer to the
following figures and tables for PM and DM memory alloca-
tions in the AD73422.
PROGRAM MEMORY
Program Memory (Full Memory Mode)
is a 24-bit-wide
space for storing both instruction op codes and data. The
AD73422-80 has 16K words of Program Memory RAM on chip
(the AD73422-40 has 8K words of Program Memory RAM on
chip), and the capability of accessing up to two 8K external
memory overlay spaces using the external data bus.
Program Memory (Host Mode)
allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16 bits wide only.
Table XXII. PMOVLAY Bits
PMOVLAY
Memory
A13
A12:0
0
1
Internal
External
Overlay 1
Not Applicable Not Applicable
0
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
Overlay 2
1
ACCESSIBLE WHEN
ACCESSIBLE WHEN
0AALWAYS
–
0x1FFF
ACPMOVLAY = 0
PM (MODE B = 0)
INTERNAL
EXTERNAL
–
0x2000
0x2000
–
0x3FFF
2
0x2000
–
0x3FFF
2
8K INTERNAL
8K EXTERNAL
PROMODE B = 1
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
8K INOR
P8K EXTERNAL
0x3FFF
0x2000
0x1FFF
8K INTERNAL
0x0000
PROMODE B = 0
ADDRESS
ACCESSIBLE WHEN
INTERNAL
EXTERNAL
–
0x2000
0x0000
–
0x1FFF
2
PM (MODE B = 1)
1
RESERVED
1
WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2
SEE TABLE III FOR PMOVLAY BITS
ACPMOVLAY = 0
RESERVED
Figure 15. Program Memory Map
DATA MEMORY
Data Memory (Full Memory Mode)
is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The AD73422-80 has 16K words on Data
Memory RAM on chip (the AD73422-40 has 8K words on Data
Memory RAM on chip), consisting of 16,352 user-accessible
locations in the case of the AD73422-80 (8,160 user-accessible
locations in the case of the AD73422-40) and 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All inter-
nal accesses complete in one cycle. Accesses to external memory
are timed using the wait states specified by the DWAIT register.
ACCESSIBLE WHEN
ACCESSIBLE WHEN
AALWAYS
0
x
2000
–
0
x
3FFF
ACDMOVLAY = 0
INTERNAL
EXTERNAL
0
x
0000
–
0
x
1FFF
0
x
0000
–
0
x
1FFF
0
x
0000
–
0
x
1FFF
DATA MEMORY
3MAPPED
REGISTERS
0
x
3FFF
0
x
2000
0
x
1FFF
IN8160
WORDS
0
x
0000
DATA MEMORY
ADDRESS
8K INOR
EXTERNAL 8K
0
x
3FE0
0
x
3FDF
Figure 16. Data Memory Map
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). The DMOVLAY bits are defined in Table XXIII.
Table XXIII. DMOVLAY Bits
DMOVLAY
Memory
A13
A12:0
0
1
Internal
External
Overlay 1
Not Applicable Not Applicable
0
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
Overlay 2
1
I/O Space (Full Memory Mode)
The AD73422 supports an additional external memory space
called I/O space. This space is designed to support simple con-
nections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table XXIV.
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