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| 型号： | AD7703AR |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 20BIT LC2MOS 20-SOIC |
| 标准包装： | 1 |
| 位数： | 20 |
| 采样率（每秒）： | 4k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 37mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极；1 个单端，双极 |
REV. E
–14–
AD7703
Synchronous Self-Clocking Mode (SSC)
The SSC mode (MODE pin high) allows easy interfacing to
serial-parallel conversion circuits in systems with parallel data
communication. This mode allows interfacing to 74XX299
Universal Shift registers without any additional decoding. The
SSC mode can also be used with microprocessors such as the
68HC11 and 68HC05, which allow an external device to clock
their serial port.
Figure 15 shows the timing diagram for the SSC mode. Data is
clocked out by an internally generated serial clock. The AD7703
divides each sampling interval into 16 distinct periods. Eight
periods of 64 clock pulses are for analog settling and eight peri-
ods of 64 clock pulses are for digital computation. The status of
CS is polled at the beginning of each digital computation period. If
it is low at any of these times, then SCLK will become active
and the data-word currently in the output register will be trans-
mitted, MSB first. After the LSB has been transmitted,
DRDY
will go high until the new data-word becomes available. If
CS,
having been brought low, is taken high again at any time during
data transmission, SDATA and SCLK will go three-state after
the current bit finishes. If
CS is subsequently brought low,
transmission will resume with the next bit during the subse-
quent digital computation period. If transmission has not been
initiated and completed by the time the next data-word is avail-
able,
DRDY will go high for four clock cycles then low again as
the new word is loaded into the output register.
A more detailed diagram of the data transmission in the SSC
mode is shown in Figure 16. Data bits change on the falling
edge of SCLK and are valid on the rising edge of SCLK.
ANALOG TIME 0
DIGITAL TIME 7
SCLK (O)
SDATA (O)
HI-Z
MSB
DRDY (O)
DIGITAL TIME 0
CS POLLED
CS (I)
INTERNAL
STATUS
72 CLKIN CYCLES
64 CLKIN
CYCLES
64 CLKIN
CYCLES
1024 CLKIN CYCLES
LSB
Figure 15. Timing Diagram for SSC Transmission Mode
CLKIN (I)
DRDY (O)
SDATA (O)
DB19 (MSB)
DB18
DB2
DB1
DB0 (LSB)
HI-Z
SCLK (O)
HI-Z
CS (I)
72
CLKIN
CYCLES
DB17
Figure 16. SSC Mode Showing Data Timing Relative to SCLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7703AR-REEL | 功能描述:IC ADC 20BIT LC2MOS MONO 20-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7703ARZ | 功能描述:IC ADC 20BIT LC2MOS 20-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7703BN | 功能描述:IC ADC 20BIT LC2MOS 20-DIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| AD7703BNZ | 功能描述:IC ADC 20BIT LC2MOS MONO 20DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD7703BQ | 制造商:AD 制造商全称:Analog Devices 功能描述:LC2MOS 20-Bit A/D Converter |
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