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| 型号： | AD7730BRU-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/53页 |
| 文件大小： | 0K |
| 描述： | IC ADC TRANSDUCER BRIDGE 24TSSOP |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 通道数： | 1 |
| 功率（瓦特）： | 125mW |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.25 V |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-AD7730LEBZ-ND - BOARD EVALUATION FOR AD7730 EVAL-AD7730EBZ-ND - BOARD EVAL FOR AD7730 |
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AD7730/AD7730L
–31–
user must write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1,
MD0 bits of the Mode Register to initiate a conversion. If
RDY is low before (or goes low during) the calibration com-
mand write to the Mode Register, it may take up to one modulator
cycle (MCLK IN/32) before
RDY goes high to indicate that
calibration is in progress. Therefore,
RDY should be ignored for
up to one modulator cycle after the last bit of the calibration
command is written to the Mode Register.
System Zero-Scale Calibration
System calibration allows the AD7730 to compensate for system
gain and offset errors as well as its own internal errors. System
calibration performs the same slope factor calculations as self-
calibration, but uses voltage values presented by the system to
the AIN inputs for the zero- and full-scale points.
A system zero-scale calibration is initiated on the AD7730 by
writing the appropriate values (1, 1, 0) to the MD2, MD1 and
MD0 bits of the Mode Register. In this calibration mode, with a
unipolar input range, the zero-scale point used in determin-
ing the calibration coefficients is the bottom end of the trans-
fer function. The system’s zero-scale point is applied to the
AD7730’s AIN input before the calibration step and this voltage
must remain stable for the duration of the system zero-scale
calibration. The PGA is set for the selected gain (as per the
RN1, RN0 bits in the Mode Register) for this system zero-scale
calibration conversion. The allowable range for the system zero-
scale voltage is discussed in the Span and Offsets Section.
The calibration is performed with either ac or dc excitation,
depending on the status of the AC bit. The duration time of the
calibration depends upon the CHP bit of the Filter Register.
With CHP = 1, the duration is 22
× 1/Output Rate; with
CHP = 0, the duration is 24
× 1/Output Rate. At this time the
MD2, MD1 and MD0 bits in the Mode Register return to
0, 0, 0 (Sync or Idle Mode for the AD7730). The
RDY line
goes high when calibration is initiated and returns low when
calibration is complete. Note that the part has not performed a
conversion at this time; it has simply performed a zero-scale
calibration and updated the Offset Calibration Register for the
selected channel. The user must write either 0, 0, 1 or 0, 1, 0 to
the MD2, MD1, MD0 bits of the Mode Register to initiate a
conversion. If
RDY is low before (or goes low during) the cali-
bration command write to the Mode Register, it may take up to
one modulator cycle (MCLK IN/32) before
RDY goes high to
indicate that calibration is in progress. Therefore,
RDY should
be ignored for up to one modulator cycle after the last bit of the
calibration command is written to the Mode Register.
For bipolar input ranges in the system zero-scale calibrating
mode, the sequence is very similar to that just outlined. In this
case, the zero-scale point is the midpoint of the AD7730’s
transfer function.
The system zero-scale calibration needs to be performed as one
part of a two part full calibration. However, once a full calibra-
tion has been performed, additional system zero-scale calibra-
tions can be performed by themselves to adjust the part’s
zero-scale point only. When performing a two-step full calibra-
tion care should be taken as to the sequence in which the two
steps are performed. If the system zero-scale calibration is one
part of a full system calibration, then it should take place before
a system full-scale calibration. If it takes place in association
with an internal full-scale calibration, then this system zero-scale
calibration should be performed after the full-scale calibration.
System Full-Scale Calibration
A system full-scale calibration is initiated on the AD7730 by
writing the appropriate values (1, 1, 1) to the MD2, MD1 and
MD0 bits of the Mode Register. System full-scale calibration is
performed using the system's positive full-scale voltage. This
full-scale voltage must be set up before the calibration is initi-
ated, and it must remain stable throughout the calibration step.
The system full-scale calibration is performed at the selected
gain (as per the RN1, RN0 bits in the Mode Register).
The calibration is performed with either ac or dc excitation,
depending on the status of the ac bit. The duration time of the
calibration depends upon the CHP bit of the Filter Register.
With CHP = 1, the duration is 22
× 1/Output Rate; with CHP =
0, the duration is 24
× 1/Output Rate. At this time the MD2,
MD1 and MD0 bits in the Mode Register return to 0, 0, 0
(Sync or Idle Mode for the AD7730). The
RDY line goes high
when calibration is initiated, and returns low when calibration is
complete. Note that the part has not performed a conversion at
this time; it has simply performed a full-scale calibration and
updated the Gain Calibration Register for the selected channel.
The user must write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1,
MD0 bits of the Mode Register to initiate a conversion. If
RDY
is low before (or goes low during) the calibration command
write to the Mode Register, it may take up to one modulator
cycle (MCLK IN/32) before
RDY goes high to indicate that
calibration is in progress. Therefore,
RDY should be ignored for
up to one modulator cycle after the last bit of the calibration
command is written to the Mode Register.
The system full-scale calibration needs to be performed as one
part of a two part full calibration. Once a full calibration has
been performed, however, additional system full-scale calibra-
tions can be performed by themselves to adjust the part's gain
calibration point only. When performing a two-step full calibra-
tion care should be taken as to the sequence in which the two
steps are performed. A system full-scale calibration should not
be carried out unless the part contains valid zero-scale coeffi-
cients. Therefore, an internal zero-scale calibration or a system
zero-scale calibration must be performed before the system full-
scale calibration when a full two-step calibration operation is
being performed.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits
on the amount of offset and span which can be accommodated.
The overriding requirement in determining the amount of offset
and gain which can be accommodated by the part is the require-
ment that the positive full-scale calibration limit is
≤1.05
× FS,
where FS is 10 mV, 20 mV, 40 mV or 80 mV depending on the
RN1, RN0 bits in the Mode Register. This allows the input
range to go 5% above the nominal range. The built-in head-
room in the AD7730’s analog modulator ensures that the part
will still operate correctly with a positive full-scale voltage that is
5% beyond the nominal.
REV. B
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| AD7730BRZ | 功能描述:IC ADC BRIDGE TRANSDUCER 24-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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