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| 型号： | AD7851KRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 333KSPS 24-SOIC |
| 标准包装： | 1,000 |
| 位数： | 14 |
| 采样率（每秒）： | 333k |
| 数据接口： | 8051，QSPI?，串行，SPI? µP |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 89.25mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极；1 个伪差分，双极 |
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AD7851
–24–
REV. B
SERIAL INTERFACE SUMMARY
Table IX details the five interface modes and the serial clock
edges from which the data is clocked out by the AD7851
(DOUT edge) and that the data is latched in on (DIN edge).
The logic level of the POLARITY pin is shown and it is clear
that this reverses the edges.
In Interface Modes 4 and 5 the
SYNC always clocks out the
first data bit and SCLK will clock out the subsequent bits.
In Interface Modes 1, 2, and 3 the
SYNC is gated with the SCLK
and the POLARITY pin. Thus, the
SYNC may clock out the
MSB of data. Subsequent bits will be clocked out by the serial
clock, SCLK. The conditions for the
SYNC clocking out the
MSB of data is as follows.
With the POLARITY pin high, the falling edge of
SYNC will
clock out the MSB if the serial clock is low when the
SYNC
goes low.
With the POLARITY pin low, the falling edge of
SYNC will
clock out the MSB if the serial clock is high when the
SYNC
goes low.
Table IX. SCLK Active Edge for Different Interface Modes
Interface
POLARITY
DOUT
DIN
Mode
Pin
Edge
1, 2, 3
0
SCLK
↑
SCLK
↓
1SCLK
↓
SCLK
↑
4, 5
0
SCLK
↓
SCLK
↑
1SCLK
↑
SCLK
↓
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. The
SYNC pin acts as a reset. Bringing the
SYNC pin high resets the internal shift register. The first data
bit after the next
SYNC falling edge will now be the first bit of
a new 16-bit transfer. It is also possible that the test register
contents were altered when the interface was lost. Therefore,
once the serial interface is reset, it may be necessary to write
the 16-bit word 0100 0000 0000 0010 to restore the test regis-
ter to its default value. Now the part and serial interface are
completely reset. It is always useful to retain the ability to pro-
gram the
SYNC line from a port of the
Controller/DSP to have
the ability to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7851. It also outlines the various
P/C to which the par-
ticular interface is suited.
The interface mode is determined by the serial mode selection
Pins SM1 and SM2. Interface Mode 2 is the default mode.
Note that Interface Mode 1 and 2 have the same combination of
SM1 and SM2. Interface Mode 1 may only be set by program-
ming the control register (see the Control Register section).
External SCLK and
SYNC signals (SYNC may be hardwired
low) are required for Interfaces Modes 1, 2, and 3. In Interface
Modes 4 and 5, the AD7851 generates the SCLK and
SYNC.
Some of the more popular
Processors, Controllers, and the
DSP machines that the AD7851 will interface to directly are
mentioned here. This does not cover all
Cs, Ps, and DSPs. The
interface mode of the AD7851 that is mentioned here for a
specific
C, P, or DSP is only a guide and in most cases another
interface mode may work just as well.
A more detailed timing description on each of the interface
modes follows.
Table X. Interface Mode Description
SM1
SM2
Processor
Interface
Pin
Controller
Mode
00
8XC51
1 (2-Wire)
8XL51
DIN Is an Input/
PIC17C42
Output Pin
00
68HC11
2 (3-Wire, SPI/QSPI)
68L11
Default Mode
01
68HC16
3 (QSPI)
PIC16C64
External Serial
ADSP-21xx
Clock, SCLK, and
DSP56000
External Frame Sync,
DSP56001
SYNC Are Required
DSP56002
DSP56L002
TMS320C30
10
68HC16
4 (DSP Is Slave)
AD7851 Generates a
Noncontinuous
(16 Clocks) Serial
Clock, SCLK, and the
Frame Sync,
SYNC
11
ADSP-21xx
5 (DSP Is Slave)
DSP56000
AD7851 Generates a
DSP56001
Continuous Serial
DSP56002
Clock, SCLK, and the
DSP56L002
Frame Sync,
SYNC
TMS320C20
TMS320C25
TMS320C30
TMS320C5X
TMS320LC5X
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