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参数资料
| 型号： | AD7851KRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 333KSPS 24-SOIC |
| 标准包装： | 1,000 |
| 位数： | 14 |
| 采样率（每秒）： | 333k |
| 数据接口： | 8051，QSPI?，串行，SPI? µP |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 89.25mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极；1 个伪差分，双极 |
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AD7851
–16–
REV. B
ANALOG INPUT
The equivalent circuit of the analog input section is shown in
Figure 11. During the acquisition interval, the switches are both
in the track position and the AIN(+) charges the 20 pF capacitor
through the 125
resistance. On the rising edge of CONVST,
Switches SW1 and SW2 go into the hold position retaining
charge on the 20 pF capacitor as a sample of the signal on
AIN(+). The AIN(–) is connected to the 20 pF capacitor, and
this unbalances the voltage at Node A at the input of the com-
parator. The capacitor DAC adjusts during the remainder of the
conversion cycle to restore the voltage at Node A to the correct
value. This action transfers a charge, representing the analog input
signal, to the capacitor DAC which in turn forms a digital repre-
sentation of the analog input signal. The voltage on the AIN(–)
pin directly influences the charge transferred to the capacitor
DAC at the hold instant. If this voltage changes during the con-
version period, the DAC representation of the analog input volt-
age will be altered. Therefore, it is most important that the voltage
on the AIN(–) pin remain constant during the conversion period.
Furthermore, it is recommended that the AIN(–) pin always be
connected to AGND or to a fixed dc voltage.
CAPACITOR
DAC
COMPARATOR
HOLD
TRACK
SW2
NODE A
20pF
SW1
TRACK
HOLD
125
AIN(+)
AIN(–)
CREF2
Figure 11. Analog Input Equivalent Circuit
Acquisition Time
The track and hold amplifier enters its tracking mode on the fall-
ing edge of the BUSY signal. The time required for the track and
hold amplifier to acquire an input signal will depend on how
quickly the 20 pF input capacitance is charged. The acquisition
time is calculated using the formula
tACQ = 9
× (R
IN + 125
) × 20 pF
where RIN is the source impedance of the input signal, and
125
, 20 pF is the input R, C.
DC/AC Applications
For dc applications, high source impedances are acceptable,
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. The acquisition time can be cal-
culated from the above formula for different source impedances.
For example, with RIN = 5 k
, the required acquisition time will
be 922 ns.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-pass
filter on the AIN(+) pin, as shown in Figure 13. In applications
where harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source. Large
source impedances will significantly affect the ac performance
of the ADC. This may necessitate the use of an input buffer
amplifier. The choice of the op amp will be a function of the
particular application.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases, and the performance will
degrade. Figure 12 shows a graph of the total harmonic distor-
tion versus the analog input signal frequency for different source
impedances. With the setup as in Figure 13, the THD is at the
–90 dB level. With a source impedance of 1 k
and no capacitor
on the AIN(+) pin, the THD increases with frequency.
THD
(dB)
INPUT FREQUENCY (kHz)
–50
–60
–110
–100
–80
–90
–70
1
166
10
20
50
80
THD VS. FREQUENCY FOR DIFFERENT
SOURCE IMPEDANCES
RIN = 560
RIN = 10 , 10nF
AS IN FIGURE 13
140
120
100
Figure 12. THD vs. Analog Input Frequency
In a single-supply application (5 V), the V+ and V– of the op amp
can be taken directly from the supplies to the AD7851 which elimi-
nates the need for extra external power supplies. When operating
with rail-to-rail inputs and outputs at frequencies greater than
10 kHz, care must be taken in selecting the particular op amp for
the application. In particular, for single-supply applications the
input amplifiers should be connected in a gain of –1 arrangement
to get the optimum performance. Figure 13 shows the arrangement
for a single-supply application with a 10
and 10 nF low-pass fil-
ter (cutoff frequency 320 kHz) on the AIN(+) pin. Note that the
10 nF is a capacitor with good linearity to ensure good ac
performance. Recommended single-supply op amp is the AD820.
IC1
5V
10k
V+
V–
10k
10
AD820
VIN
–VREF/2 TO +VREF/2
VREF/2
10 F
0.1 F
10nF
(NPO)
TO AIN(+) OF
AD7851
Figure 13. Analog Input Buffering
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