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参数资料
| 型号： | AD7851KRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 333KSPS 24-SOIC |
| 标准包装： | 1,000 |
| 位数： | 14 |
| 采样率（每秒）： | 333k |
| 数据接口： | 8051，QSPI?，串行，SPI? µP |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 89.25mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极；1 个伪差分，双极 |
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–25–
REV. B
AD7851
DB15
DB0
DB15
t
3
DIN (I/O)
t
3
t
11
t
6
116
16
1
t
5A
t
12
DIN BECOMES AN INPUT
THREE-STATE
t
6
t
11
DIN BECOMES AN OUTPUT
t
3 = –0.4 tSCLK MIN (NONCONTINUOUS SCLK)
0.4 t
SCLK MIN/MAX (CONTINUOUS SCLK),
t
6 = 45 MAX, t7 = 30ns MIN, t8 = 20 MIN
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
t
8
t
14
t
7
DATA WRITE
DATA READ
Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (Interface Mode 1, SM1 = SM2 = 0)
DB15
DB0
DB15
DIN (I/O)
t
6 = 45 MAX, t7 = 30ns MIN, t8 = 20 MIN,
t
13 = 90 MAX, t14 = 50ns MAX
6
116
16
1
t
13
t
6
DIN BECOMES AN INPUT
t
6
POLARITY PIN
LOGIC HIGH
SCLK (I/P)
t
8
t
14
t
7
DATA WRITE
DATA READ
Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and
SYNC Input Tied Low
(Interface Mode 1, SM1 = SM2 = 0)
DETAILED TIMING SECTION
Mode 1 (2-Wire 8051 Interface)
The read and writing takes place on the DIN line and the conver-
sion is initiated by pulsing the
CONVST pin (note that in every
write cycle the 2/
3 MODE bit must be set to 1). The conversion
may be started by setting the
CONVST bit in the control register
to 1 instead of using the
CONVST line.
Below in Figure 33 and in Figure 34 are the timing diagrams for
Interface Mode 1 in the 2-wire interface mode. Here the DIN pin
is used for both input and output as shown. The
SYNC input is
level-triggered active low and can be pulsed (Figure 33) or can be
constantly low (Figure 34).
In Figure 33, the part samples the input data on the rising edge
of SCLK. After the 16th rising edge of SCLK, the DIN is con-
figured as an output. When the
SYNC is taken high, the DIN is
three-stated. Taking
SYNC low disables the three-state on the
DIN pin and the first SCLK falling edge clocks out the first data
bit. Once the 16 clocks have been provided, the DIN pin will
automatically revert back to an input after a time t14. Note that a
continuous SCLK shown by the dotted waveform in Figure 33
can be used provided the
SYNC is low for only 16 clock pulses
in each of the read and write cycles. The POLARITY pin may
be used to change the SCLK edge which the data is sampled on
and clocked out on.
In Figure 34, the
SYNC line is tied low permanently, which
results in a different timing arrangement. With
SYNC tied low
permanently, the DIN pin will never be three-stated. The 16th
rising edge of SCLK configures the DIN pin as an input or an
output as shown in the diagram. Here no more than 16 SCLK
pulses must occur for each of the read and write operations.
If reading from and writing to the calibration registers in this
interface mode, all the selected calibration registers must be
read from or written to. The read and write operations cannot
be aborted. When reading from the calibration registers, the
DIN pin will remain as an output for the full duration of all
the calibration register read operations. When writing to the
calibration registers, the DIN pin will remain as an input for
the full duration of all the calibration register write operations.
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