- 您现在的位置：买卖IC网 > PDF目录10243 > AD7853LARS-REEL (Analog Devices Inc)IC ADC 12BIT SRL 200KSPS 24-SSOP PDF资料下载
参数资料
| 型号： | AD7853LARS-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 200KSPS 24-SSOP |
| 标准包装： | 1,500 |
| 位数： | 12 |
| 采样率（每秒）： | 100k |
| 数据接口： | 8051，QSPI?，串行，SPI? µP |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 33mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极；1 个伪差分，双极 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
REV. B
–21–
AD7853/AD7853L
capacitors, one of which is trimmed when an offset or gain cali-
bration is performed. Again it is the ratio of these capacitors to
the capacitors in the DAC that is critical and the calibration
algorithm ensures that this ratio is at a specified value for both
the offset and gain calibrations.
In Bipolar Mode the midscale error is adjusted for an offset
calibration and the positive full-scale error is adjusted for the
gain calibration; in Unipolar Mode the zero-scale error is ad-
justed for an offset calibration and the positive full-scale error is
adjusted for a gain calibration.
Self-Calibration Timing
The diagram of Figure 27 shows the timing for a full self-
calibration. Here the BUSY line stays high for the full length of
the self-calibration. A self-calibration is initiated by bringing the
CAL pin low (which initiates an internal reset) and then high
again or by writing to the control register and setting the STCAL
bit to 1 (note that if the part is in a power-down mode, the
CAL
pulsewidth must take account of the power-up time). The BUSY line
is triggered high from the rising edge of
CAL (or the end of the
write to the control register if calibration is initiated in soft-
ware), and BUSY will go low when the full self-calibration is
complete after a time tCAL as shown in Figure 27.
t1 = 100ns MIN,
t15 = 2.5 tCLKIN MAX,
tCAL = 125013 tCLKIN
(I/P)
BUSY (O/P)
t1
t15
tCAL
Figure 27. Timing Diagram for Full Self-Calibration
For the self-(gain + offset), self-offset and self-gain calibrations,
the BUSY line will be triggered high by the rising edge of the
CAL signal (or the end of the write to the control register if
calibration is initiated in software) and will stay high for the full
duration of the self-calibration. The length of time that the
BUSY is high for will depend on the type of self-calibration that
is initiated. Typical figures are given in Table IX. The timing
diagrams for the other self-calibration options will be similar to
that outlined in Figure 27.
System Calibration Description
System calibration allows the user to take out system errors
external to the AD7853/AD7853L as well as calibrate the errors
of the AD7853/AD7853L itself. The maximum calibration
range for the system offset errors is
±5% of V
REF and for the
system gain errors is
±2.5% of V
REF. This means that the maxi-
mum allowable system offset voltage applied between the
AIN(+) and AIN(–) pins for the calibration to adjust out this
error is
±0.05 × V
REF (i.e., the AIN(+) can be 0.05 × VREF above
AIN(–) or 0.05
× V
REF below AIN(–)). For the system gain error
the maximum allowable system full-scale voltage, in unipolar
mode, that can be applied between AIN(+) and AIN(–) for the
calibration to adjust out this error is VREF
± 0.025 × V
REF (i.e.,
the AIN(+) can be VREF + 0.025
× V
REF above AIN(–) or VREF –
0.025
× V
REF above AIN(–)). If the system offset or system gain
errors are outside the ranges mentioned, the system calibration
algorithm will reduce the errors as much as the trim range allows.
Figures 33 through 35 illustrate why a specific type of system
calibration might be used. Figure 33 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be accounted for by a system offset calibration.
MAX SYSTEM FULL SCALE
IS
2.5% FROM VREF
ANALOG
INPUT
RANGE
VREF – 1LSB
SYS OFFSET
AGND
VREF + SYS OFFSET
MAX SYSTEM OFFSET
IS
5% OF VREF
ANALOG
INPUT
RANGE
VREF – 1LSB
SYS OFFSET
AGND
SYSTEM OFFSET
CALIBRATION
MAX SYSTEM OFFSET
IS
5% OF VREF
Figure 28. System Offset Calibration
Figure 29 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
MAX SYSTEM FULL SCALE
IS
2.5% FROM VREF
ANALOG
INPUT
RANGE
VREF – 1LSB
AGND
SYS FULL S.
ANALOG
INPUT
RANGE
VREF – 1LSB
SYS FULL S.
AGND
SYSTEM GAIN
CALIBRATION
MAX SYSTEM FULL SCALE
IS
2.5% FROM VREF
Figure 29. System Gain Calibration
Finally in Figure 30 both the system offset and gain are ac-
counted for by the system offset followed by a system gain cali-
bration. First the analog input range is shifted upwards by the
positive system offset and then the analog input range is ad-
justed at the top end to account for the system full scale.
ANALOG
INPUT
RANGE
SYS F.S.
SYS OFFSET
VREF + SYS OFFSET
ANALOG
INPUT
RANGE
VREF – 1LSB
SYS F. S.
AGND
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
SYSTEM GAIN
CALIBRATION
MAX SYSTEM FULL SCALE
IS
2.5% FROM VREF
SYS OFFSET
MAX SYSTEM OFFSET
IS
5% OF VREF
MAX SYSTEM OFFSET
IS
5% OF VREF
AGND
VREF – 1LSB
MAX SYSTEM FULL SCALE
IS
2.5% FROM VREF
Figure 30. System (Gain + Offset) Calibration
相关PDF资料 |
PDF描述 |
|---|---|
| VE-23T-CU-F4 | CONVERTER MOD DC/DC 6.5V 200W |
| VE-B2M-MW-F4 | CONVERTER MOD DC/DC 10V 100W |
| VI-26F-MY | CONVERTER MOD DC/DC 72V 50W |
| VE-B2M-MW-F3 | CONVERTER MOD DC/DC 10V 100W |
| VE-23R-IW-S | CONVERTER MOD DC/DC 7.5V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7853LARSZ | 功能描述:IC ADC 12BIT SRL 200KSPS 24SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7853LARSZ-REEL | 功能描述:IC ADC 12BIT SRL 200KSPS 24SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7853LARZ | 功能描述:IC ADC 12BIT SRL 200KSPS 24SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7853LARZ-REEL | 功能描述:IC ADC 12BIT SRL 200KSPS 24SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| AD7853LBN | 功能描述:IC ADC 12BIT SRL 200KSPS 24-DIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
发布紧急采购，3分钟左右您将得到回复。