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| 型号： | AD7949BCPZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 250KSPS 8CH 20LFCSP |
| 产品培训模块： | Power Line Monitoring |
| 产品变化通告： | Startup Circuitry Design Improvement Change 15/April/2009 |
| 标准包装： | 1,500 |
| 系列： | PulSAR® |
| 位数： | 14 |
| 采样率（每秒）： | 250k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 15.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | * |
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Data Sheet
AD7949
Rev. D | Page 25 of 32
GENERAL TIMING WITHOUT A BUSY INDICATOR
Figure 36 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC),
and read/write spanning conversion (RSC). Note that the gating
item for both CFG and data readback is at the end of conversion
(EOC). At EOC, if CNV is high, the busy indicator is disabled.
As detailed previously in the Digital Interface section, the data
access should occur up to safe data reading/writing time, tDATA.
If the full CFG word was not written to prior to EOC, it is dis-
carded and the current configuration remains. If the conversion
result is not read out fully prior to EOC, it is lost as the ADC
updates SDO with the MSB of the current conversion. For
detailed timing, refer to Figure 39 and Figure 40, which depict
reading/writing spanning conversion with all timing details,
including setup, hold, and SCK.
When CNV is brought low after EOC, SDO is driven from high
impedance to the MSB. Falling SCK edges clock out bits starting
with MSB 1.
The SCK can idle high or low depending on the clock polarity
(CPOL) and clock phase (CPHA) settings if SPI is used. A simple
solution is to use CPOL = CPHA = 0 as shown in Figure 36 with
SCK idling low.
From power-up, in any read/write mode, the first three conver-
sion results are undefined because a valid CFG does not take
place until the 2nd EOC; thus two dummy conversions are
required. Also, if the state machine writes the CFG during the
power-up state (RDC shown), the CFG register needs to be
rewritten again at the next phase. Note that the first valid data
occurs in Phase (n + 1) when the CFG register is written during
Phase (n 1).
ACQUISITION
(n – 1) UNDEFINED
ACQUISITION
(n)
ACQUISITION
(n + 1)
ACQUISITION
(n + 2)
PHASE
POWER
UP
EOC
SOC
EOC
CONVERSION
(n – 1) UNDEFINED
CONVERSION
(n)
CONVERSION
(n + 1)
CONVERSION
(n – 2) UNDEFINED
tCONV
tCYC
tDATA
CNV
DIN
SDO
XXX
MSB
XXX
MSB
XXX
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
2. A TOTAL OF 14 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 28 SCK FALLING EDGES IS
REQUIRED TO RETURN SDO TO HIGH-Z.
3. WITH THE SEQUENCER ENABLED, THE NEXT ACQUISITION PHASE WILL BE FOR IN0 AFTER THE LAST CHANNEL SET IN CFG[9:7] IS CONVERTED.
DATA (n)
DATA (n – 1)
XXX
DATA (n – 1)
XXX
DATA (n – 1)
XXX
DATA (n – 1)
XXX
DATA (n – 2)
XXX
DATA (n – 2)
XXX
DATA (n – 2)
XXX
DATA (n – 2)
XXX
DATA (n – 3)
XXX
MSB
(n)
DIN
SDO
DATA (n + 1)
DATA (n)
DATA (n + 1)
DIN
CFG (n)
CFG (n + 2)
CFG (n + 1)
CFG (n + 3)
SDO
SCK
1
14
1
SCK
1
14
n
nnn
n + 1
1
SCK
1
14
1
CFG (n)
CFG (n + 1)
CFG (n + 2)
RDC
RAC
RSC
CFG (n)
CFG (n + 1)
CFG (n + 2)
CFG (n + 3)
14
07
35
1-
0
3
6
NOTE 1
NOTE 2
Figure 36. General Interface Timing for the AD7949 Without a Busy Indicator
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