参数资料
| 型号： | AD8384ASVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/24页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER LCD 6CH 10BIT 80-TQFP |
| 产品变化通告： | AD8384ASVZ Discontinuation 28/Feb/2012 |
| 标准包装： | 1 |
| 系列： | DecDriver™ |
| 显示器类型： | LCD |
| 接口： | 3 线串口 |
| 电流 - 电源： | 40mA |
| 电源电压： | 9 V ~ 18 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP-EP（12x12） |
| 包装： | 托盘 |
AD8384
SPECIFICATIONS
DecDriver
Table 1. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T A MIN = 0°C, T A MAX = 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V,
unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Unit
VIDEO DC PERFORMANCE 1
T A MIN to T A MAX
VDE
VCME
DAC Code 450 to 800
DAC Code 450 to 800
–7.5
–3.5
+7.5
+3.5
mV
mV
VIDEO OUTPUT DYNAMIC PERFORMANCE
T A MIN to T A MAX , V O = 5 V Step, C L = 150 pF
Data Switching Slew Rate
Invert Switching Slew Rate
20% to 80%
20% to 80%
460
560
V/μs
V/μs
Data Switching Settling Time to 1%
Data Switching Settling Time to 0.25%
19
30
24
50
ns
ns
Invert Switching Settling Time to 1%
Invert Switching Settling Time to 0.25%
Invert Switching Overshoot
CLK and Data Feedthrough 2
V O = 10 V Step
V O = 10 V Step
V O = 10 V Step
75
250
100
10
120
500
200
ns
ns
mV
mV p-p
All-Hostile Crosstalk 3
Amplitude
Glitch Duration
10
30
mV p-p
ns
DAC Transition Glitch Energy
DAC Code 511 to 512
0.3
nV-s
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage—Grounded Mode
AVCC – VOH, VOL – AGND
1.1
0.25
1.3
V
V
Data Switching Delay: t 94
INV Switching Delay: t 105
50 % of VIDx
50 % of VIDx
10
13
12
15
14
17
ns
ns
Output Current
Output Resistance
REFERENCE INPUTS
100
22
mA
?
V1 Range
V2 Range
V1 Input Current
V2 Input Current
VRL Range
VRH Range
(VRH–VRL) Range
VRH Input Resistance
VRL Bias Current
VRH Input Current
V2 ≥ (V1-0.25V)
V2 ≥ (V1-0.25V)
VRH ≥ VRL
VRH ≥ VRL
VFS = 2(VRH – VRL)
To VRL
5.25
5.25
V1 – 0.5
VRL
0
–3
–14
20
–0.2
125
AVCC – 4
AVCC – 4
AVCC – 1.3
AVCC
2.75
V
V
μA
μA
V
V
V
k?
μA
μA
RESOLUTION
Coding
Binary
10
Bits
1
2
3
4
5
VDE = differential error voltage; VCME = common-mode error voltage; VFS = full-scale output voltage = 2 × (VRH – VRL). See the Accuracy section.
Measured differentially on two outputs as CLK and DB(0:9) are driven and STSQ and XFR are held LOW.
Measured differentially on two outputs as the other four are transitioning by 5 V. Measured for both states of INV.
Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV.
Measured from 50% of rising CLK edge to 50% of output change. Refer to Figure 7 for the definition.
Rev. 0 | Page 3 of 24
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