参数资料
| 型号： | AD8384ASVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER LCD 6CH 10BIT 80-TQFP |
| 产品变化通告： | AD8384ASVZ Discontinuation 28/Feb/2012 |
| 标准包装： | 1 |
| 系列： | DecDriver™ |
| 显示器类型： | LCD |
| 接口： | 3 线串口 |
| 电流 - 电源： | 40mA |
| 电源电压： | 9 V ~ 18 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP-EP（12x12） |
| 包装： | 托盘 |
AD8384
SERIAL INTERFACE
Table 4. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T A MIN = 0°C, T A MAX = 85°C, SVRL = 4 V, SVR H = 9 V, unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Unit
SERIAL DAC REFERENCE INPUTS
SVFS = (SVRH – SVRL)
SVRH Range
SVRL Range
SVRL < SVRH
SVRL < SVRH
SVRL + 1
AGND + 1.5
AVCC – 3.5
SVRH – 1
V
V
SVFS Range
SVRH Input Current
SVFS = 5 V
1
–70
8
V
nA
SVRL Input Current
SVRH Input Resistance
SVFS = 5 V
–2.8
–2.5
40
mA
k?
SERIAL DAC ACCURACY
DNL
INL
Output Offset Error
Scale Factor Error
SVFS = 5 V, R L = ∞
SVFS=5 V, R L = ∞
–1.0
–1.5
–2.0
–4.0
+1.0
+1.5
+2.0
+4.0
LSB
LSB
LSB
LSB
SERIAL DAC LOGIC INPUTS
C IN
I IL
I IH
V TH
–0.6
0.05
1.65
3
pF
μA
μA
V
V IH
V IL
2.0
DGND
DVCC
0.8
V
V
SERIAL DAC OUTPUTS
Maximum Output Voltage
Minimum Output Voltage
VAO1—Grounded Mode
I OUT
C LOAD Low Range 6
C LOAD High Range 1
SERIAL DAC DYNAMIC PERFORMANCE
SEN to SCL Setup Time, t 20
SCL, High Level Pulse Width, t 21
SCL, Low Level Pulse Width, t 22
SDI Setup Time, t 24
SDI Hold Time, t 25
SCL to SEN Hold Time, t 23
0.047
10
15
10
10
10
15
SVRH – 1 LSB
SVRL
0.1
±30
0.002
V
V
V
mA
μF
μF
ns
ns
ns
ns
ns
ns
VAO1, VAO2 Settling Time, t 26
VAO1, VAO2 Settling Time, t 26
SVFS = 5 V, to 0.5%, C L = 100 pF
SVFS = 5 V, to 0.5%, C L = 33 μF
1
10
2
15
μs
ms
6
Outputs VAO1 and VAO2 are designed to drive very high capacitive loads. The load capacitance must be ≤ 0.002 μF or ≥ 0.047 μF.
Load capacitance in the range 0.002 μF to 0.047 μF causes the output overshoot to exceed 100 mV.
Rev. 0 | Page 6 of 24
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