参数资料
| 型号： | AD8384ASVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/24页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER LCD 6CH 10BIT 80-TQFP |
| 产品变化通告： | AD8384ASVZ Discontinuation 28/Feb/2012 |
| 标准包装： | 1 |
| 系列： | DecDriver™ |
| 显示器类型： | LCD |
| 接口： | 3 线串口 |
| 电流 - 电源： | 40mA |
| 电源电压： | 9 V ~ 18 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP-EP（12x12） |
| 包装： | 托盘 |
AD8384
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DGND 1
TSTM 2
CLK 3
XFR 4
STSQ 5
INV 6
R/L 7
E/O 8
SDI 9
SEN 10
SCL 11
NC 12
AGNDS 13
SVRL 14
SVRH 15
VAO1 16
VAO2 17
AVCCS 18
DIRXIN 19
DIRYIN 20
PIN 1
IDENTIFIER
AD8384
TOP VIEW
(Not to Scale)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AGND0
VID0
AVCC0,1
VID1
AGND1,2
VID2
AVCC2,3
VID3
AGND3,4
VID4
AVCC4,5
VID5
AGND5
CLXN
CLX
ENBX4
ENBX3
ENBX2
ENBX1
DX
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC =
NO CONNECT
Figure 3. 80-Lead 12 mm × 12 mm TQFP E-Pad Pin Configuration
Table 7. Pin Function Descriptions
Pin Name
DB(0:9)
CLK
STSQ
R/L
E/O
XFR
VID0–VID5
V1, V2
VRH, VRL
BYP
Function
Data Input
Clock
Start Sequence
Right/Left Select
Even/Odd Select
Data Transfer
Analog Outputs
Reference Voltages
Full-Scale References
Bypass
Description
10-Bit Data Input. MSB = DB(9).
Clock Input.
The state of STSQ is detected on the active edge of CLK. A new data loading sequence
begins on the next active edge of CLK after STSQ is detected HIGH.
The active CLK edge is the rising edge when E/O is held HIGH. It is the falling edge when
E/O is held LOW.
A new data loading sequence begins on the left, with Channel 0, when this input is LOW,
and on the right, with Channel 5, when this input is HIGH.
The active CLK edge is the rising edge when this input is held HIGH. It is the falling edge
when this input is held LOW. Data is loaded sequentially on the rising edges of CLK when
this input is HIGH and on the falling edges when this input is LOW.
XFR is detected and a data transfer is initiated on a rising CLK edge when this input is held
HIGH. Data is transferred to the video outputs on the next rising CLK edge after XFR is
detected.
These pins are directly connected to the analog inputs of the LCD panel.
The voltage applied between V1 and AGND sets the white video level during INV = LOW.
The voltage applied between V2 and AGND sets the white video level during INV = HIGH.
Twice the voltage applied between these pins sets the full-scale video output voltage.
A 0.1μ F capacitor connected between this pin and AGND ensures optimum settling time.
Rev. 0 | Page 9 of 24
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