- 您现在的位置：买卖IC网 > PDF目录17099 > AD9148-EBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9148 PDF资料下载
参数资料
| 型号： | AD9148-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 51/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9148 |
| 设计资源： | AD9148-EBZ Schematic AD9148-EBZ BOM AD9148-EBZ Gerber Files |
| 标准包装： | 1 |
| 系列： | TxDAC+® |
| DAC 的数量： | 4 |
| 位数： | 16 |
| 采样率（每秒）： | 1G |
| 数据接口： | 串行，SPI? |
| 设置时间： | 20ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9148 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页当前第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
Data Sheet
AD9148
Rev. B | Page 55 of 72
When using the fine modulator, the maximum signal bandwidth of
0.8 × fDATA is always achieved.
Updating the Frequency Tuning Word
The frequency tuning word registers are not updated immediately
upon writing as the other configuration registers do. After loading
the FTW registers with the desired values, Bit 2 of Register 0x5A
must transition from 0 to 1 for the new FTW to take effect.
Phase Offset Adjustment
A 16-bit phase offset may be added to the output of the phase
accumulator via the serial port. This static phase adjustment
results in an output signal that is offset by a constant angle
relative to the nominal signal. This allows the user to phase
align the NCO output with some external signal, if necessary.
This can be especially useful when NCOs of multiple AD9148s
are programmed for synchronization. The phase offset allows
for the adjustment of the output timing between the devices.
The static phase adjustment is sourced from the NCO Phase
Offset[15:0] value located in Register 0x58 and Register 0x59.
QUADRATURE PHASE CORRECTION
The purpose of the quadrature phase correction block is to
enable compensation of the phase imbalance of the analog
quadrature modulator following the DAC. If the quadrature
modulator has a phase imbalance, the unwanted sideband
appears with significant energy. Tuning the quadrature
phase adjust value can optimize image rejection in single
sideband radios.
Ordinarily, the I and Q channels have an angle of precisely 90°
between them. The quadrature phase adjustment is used to
change the angle between the I and Q channels. When I Phase
Adj, Bits[9:0] (Register 0x28 and Register 0x29), are set to
1000000000b, the I DAC output moves approximately 1.75°
away from the Q DAC output, creating an angle of 91.75°
between the channels. When I Phase Adj, Bits[9:0] (Register 0x28
and Register 0x29), are set to 0111111111b, the I DAC output
moves approximately 1.75° toward the Q DAC output, creating
an angle of 88.25° between the channels.
Q Phase Adj, Bits[9:0] (Register 2A and Register 2B), work in a
similar fashion. When Q Phase Adj, Bits[9:0] (Register 2A and
Register 2B), are set to 1000000000b, the Q DAC output moves
approximately 1.75° away from the I DAC output, creating an
angle of 91.75° between the channels. When Q Phase Adj[9:0]
is set to 0111111111b, the Q DAC output moves approximately
1.75° toward the I DAC output, creating an angle of 88.25°
between the channels.
Based on these two endpoints, the combined resolution of
the phase compensation register is approximately 3.5°/1024 or
0.00342° per code. When both I Phase Adj, Bits[9:0] (Register 0x28
and Register 0x29), and Q Phase Adj, Bits[9:0] (Register 2A and
Register 2B), are used, the full phase adjustment range is ±3.5°.
DC OFFSET CORRECTION
The dc value of the I data path and the Q data path can be
independently controlled by adjusting I DC Offset, Bits[15:0],
and Q DC Offset, Bits[15:0], values in Register 0x2C through
Register 0x2F. These values are added directly to the data path
values. Care should be taken not to overrange the transmitted
values.
Figure 72 shows how the DAC offset current varies as a function of
I DC Offset, Bits[15:0], and Q DC Offset, Bits[15:0], values. With
the digital inputs fixed at midscale (0x000, twos complement
currents as the DC offset value is swept from 0 to 65,535.
Because IOUTxP and IOUTxN are complementary current outputs,
the sum of IOUTxP and IOUTxN is always 20 mA.
0x0000
0x4000
0x8000
0xC000
0xFFFF
5
10
15
20
5
10
15
20
0
DAC OFFSET VALUE
I O
UT
x
N
(mA)
I O
UT
x
P
(
mA)
08910-
131
Figure 72. DAC Output Currents vs. DC Offset Value
DIGITAL GAIN CONTROL
The last block in each datapath is an 8-bit scalar (Register 0x50
and Register 0x51) that can be used for digital gain control. The
IGain Control, Bits[7:0] (Register 0x50), and QGain control,
Bits[7:0] (Register 0x51), values directly scale the samples written to
the IDAC and QDAC, respectively. The bit weighting is MSB = 21
and LSB = 2-6, which yields a multiplier range of 0 to 3.984375.
The scale factor for each data path is calculated as
64
]
0
:
7
[
64
]
0
:
7
[
QGain
or
IGain
r
ScaleFacto =
Take care not to overrange the DAC when using a scale factor
greater than 1.
相关PDF资料 |
PDF描述 |
|---|---|
| SCRH124-150 | INDUCTOR SMD 15UH 3.20A 100KHZ |
| SCRH6D28-470 | INDUCTOR SMD 47UH 0.80A 10KHZ |
| 0982660828 | CBL 13POS 0.5MM JMPR TYPE D 10" |
| HCM12DSEN-S243 | CONN EDGECARD 24POS .156 EYELET |
| RBM12DCAD | CONN EDGECARD 24POS R/A .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9148-M5372-EBZ | 功能描述:BOARD EVAL FOR AD9149, ADL5372 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148-M5375-EBZ | 功能描述:BOARD EVAL FOR AD9149, ADL5375 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9152BCPZ | 功能描述:16 Bit Digital to Analog Converter 2 56-LFCSP-WQ (8x8) 制造商:analog devices inc. 系列:TxDAC+? 包装:托盘 零件状态:有效 位数:16 数模转换器数:2 建立时间:- 输出类型:Current - Unbuffered 差分输出:是 数据接口:JESD204B 参考类型:内部 电压 - 电源，模拟:3.13 V ~ 3.47 V 电压 - 电源，数字:1.14 V ~ 1.26 V INL/DNL（LSB）:±10，±5 架构:电流源 工作温度:-40°C ~ 85°C 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:1 |
| AD9152BCPZRL | 功能描述:16 Bit Digital to Analog Converter 2 56-LFCSP-WQ (8x8) 制造商:analog devices inc. 系列:TxDAC+? 包装:带卷（TR） 零件状态:有效 位数:16 数模转换器数:2 建立时间:- 输出类型:Current - Unbuffered 差分输出:是 数据接口:JESD204B 参考类型:内部 电压 - 电源，模拟:3.13 V ~ 3.47 V 电压 - 电源，数字:1.14 V ~ 1.26 V INL/DNL（LSB）:±10，±5 架构:电流源 工作温度:-40°C ~ 85°C 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:2,500 |
| AD9152-EBZ | 功能描述:AD9152 TxDAC+? Series 16 Bit 2.25G Samples Per Second Digital to Analog Converter (DAC) Evaluation Board 制造商:analog devices inc. 系列:TxDAC+? 零件状态:有效 DAC 数:2 位数:16 采样率（每秒）:2.25G 数据接口:SPI 建立时间:- DAC 类型:电流 工作温度:-40°C ~ 85°C 所含物品:板，线缆 使用的 IC/零件:AD9152 标准包装:1 |
发布紧急采购，3分钟左右您将得到回复。