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参数资料
| 型号： | AD9148-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 53/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9148 |
| 设计资源： | AD9148-EBZ Schematic AD9148-EBZ BOM AD9148-EBZ Gerber Files |
| 标准包装： | 1 |
| 系列： | TxDAC+® |
| DAC 的数量： | 4 |
| 位数： | 16 |
| 采样率（每秒）： | 1G |
| 数据接口： | 串行，SPI? |
| 设置时间： | 20ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9148 |
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Data Sheet
AD9148
Rev. B | Page 57 of 72
CLK_P/CLK_N
(PIN B6 AND PIN A6)
ADC
VCO
LOOP
FILTER
REFCLK_P/REFCLK_N
(PIN B9 AND PIN A9)
0x0E[3:0]
PLL CONTROL
VOLTAGE
0x0D[1:0]
N1
0x0D[3:2]
N0
0x0D[7:6]
N2
÷N1
÷N0
0x06[7:6]
PLL LOCK
PLL LOCK LOST
PHASE
DETECTION
0x0A[7]
PLL ENABLE
DACCLK
PC_CLK
÷N2
08910-
072
Figure 74. PLL Clock Multiplication Circuit
Table 25. PLL Settings
Address
PLL SPI Control
Register
Bit
Optimal Setting
PLL Loop Bandwidth
0x0C
[7:5]
110
PLL Control 1 Register
0x0C
[4:0]
01001
PLL Cross Control Enable
0x0D
[4]
1
CLOCK MULTIPLICATION
The on-chip PLL clock multiplier circuit can be used to generate
the DAC sample rate clock from a lower frequency reference clock.
When the PLL clock multiplier is enabled (Register 0x0A[7] = 1),
the clock multiplication circuit generates the DAC sample clock
from the lower rate REFCLK input. The functional diagram of
the clock multiplier is shown in Figure 74.
The clock multiplication circuit operates such that the VCO
outputs a frequency, fVCO, equal to the REFCLK input signal
frequency multiplied by N0 × N1.
fVCO = fREFCLK × (N0 × N1)
The DAC sample clock frequency, fDACCLK, is equal to
fDACCLK = fREFCLK × N1
The output frequency of the VCO must be chosen to keep fVCO in
the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency
of the reference clock and the values of N1 and N0 must be chosen
so that the desired DACCLK frequency can be synthesized and
the VCO output frequency is in the correct range.
PLL Bias Settings
There are four bias settings for the PLL circuitry that should be
programmed to their nominal values. The PLL values shown in
Table 25 are the recommended settings for these parameters.
Configuring the VCO Tuning Band
The PLL VCO has a valid operating range from approximately
1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands.
For any desired VCO output frequency, there may be several
valid PLL band select values. The frequency bands of a typical
device are shown in Figure 75. Device-to-device variations and
operating temperature affect the actual band frequency range.
Therefore, it is required that the optimal PLL band select value
be determined for each individual device.
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
1000
2200
2000
1800
1600
1400
1200
P
L
BAND
VCO FREQUENCY (MHz)
08910-
073
Figure 75. PLL Lock Range Overtemperature for a Typical Device
Automatic VCO Band Select
The device has an automatic VCO band select feature on chip;
using this feature is a simple and reliable method for configuring
the VCO frequency band. To use the automatic VCO band select
feature, enable the PLL by writing 0xC0 to Register 0x0A and
enable the auto band select mode by writing 0x80 to Register 0x0A.
When this value is written, the device executes an automated
routine that determines the optimal VCO band setting for the
device. The setting selected by the device ensures that the PLL
remains locked over the full 40°C to +85°C operating temperature
range of the device without further adjustment. (The PLL remains
locked over the full temperature range even if the temperature
during initialization is at one of the temperature extremes.)
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