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参数资料
| 型号： | AD9244BSTZRL-65 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SGL 65MSPS 48LQFP |
| 标准包装： | 2,000 |
| 位数： | 14 |
| 采样率（每秒）： | 65M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 550mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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AD9244
Rev. C | Page 23 of 36
Clock Input Modes
clock receiver. Figure 55 shows a differential clock directly
coupled to CLK+ and CLK–. In this mode, the common mode
of the CLK+ and CLK– signals should be close to 1.6 V. Figure 56
illustrates a single-ended clock input. The capacitor decouples
the internal bias voltage on the CLK– pin (about 1.6 V), estab-
lishing a threshold for the CLK+ pin. Figure 57 provides
backward compatibility with the AD9226. In this mode, CLK
is grounded, and the threshold for CLK+ is 1.5 V. Figure 58
shows a differential clock ac-coupled by connecting through
two capacitors. AC coupling a single-ended clock can also be
accomplished using the circuit in Figure 59.
When using the differential clock circuits of Figure 55 or Figure 58,
if CLK drops below 250 mV, the mode of the clock receiver
may change, causing conversion errors. It is essential that CLK
remains above 250 mV when the clock is ac-coupled or dc-coupled.
Clock Input Considerations
The analog input is sampled on the rising edge of the clock.
Timing variations, or jitter, on this edge causes the sampled
input voltage to be in error by an amount proportional to the
slew rate of the input signal and to the amount of the timing
variation. Thus, to maintain the excellent high frequency SFDR
and SNR characteristics of the AD9244, it is essential that the
clock edge be kept as clean as possible.
The clock should be treated like an analog signal. Clock drivers
should not share supplies with digital logic or noisy circuits.
The clock traces should not run parallel to noisy traces. Using a
pair of symmetrically routed, differential clock signals can help
to provide immunity from common-mode noise coupled from
the environment.
The clock receiver functions like a differential comparator. At
the CLK inputs, a slowly changing clock signal results in more
jitter than a rapidly changing one. Driving the clock with a low
amplitude sine wave input is not recommended. Running a high
speed clock through a divider circuit provides a fast rise/fall
time, resulting in the lowest jitter in most systems.
CLK+
CLK–
AD9244
02404-055
Figure 55. Differential Clock Input, DC-Coupled
AGND
0.1
μF
1.6V
CLK+
CLK–
AD9244
02404-056
Figure 56. Single-Ended Clock Input, DC-Coupled
AGND
CLK+
CLK–
AD9244
02404-057
Figure 57. Single-Ended Input, Retains Pin Compatibility with AD9226
100pF
TO 0.1
μF
CLK+
CLK–
AD9244
02404-058
Figure 58. Differential Clock Input, AC-Coupled
0.1
μF
AGND
0.1
μF
1.6V
CLK+
CLK–
AD9244
02404-059
Figure 59. Single-Ended Clock Input, AC-Coupled
Clock Power Dissipation
Most of the power dissipated by the AD9244 is from the analog
power supplies. However, lower clock speeds reduce digital
supply current. Figure 60 shows the relationship between power
and clock rate.
02404-060
SAMPLE RATE (MHz)
70
010
30
40
20
50
60
P
O
WE
R
(mW)
600
550
500
450
400
350
300
250
200
AD9244-40
AD9244-65
Figure 60. Power Consumption vs. Sample Rate
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9244BSTZRL-651 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD9244-EVAL | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 40/65 MSPS Monolithic A/D Converter |
| AD9245 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCP-20EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
| AD9245BCP-20EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9245 3 V A/D Converter,14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
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