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| 型号： | AD9244BSTZRL-65 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SGL 65MSPS 48LQFP |
| 标准包装： | 2,000 |
| 位数： | 14 |
| 采样率（每秒）： | 65M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 550mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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AD9244
Rev. C | Page 17 of 36
THEORY OF OPERATION
The AD9244 is a high performance, single-supply 14-bit ADC.
In addition to high dynamic range Nyquist sampling, it is
designed for excellent IF undersampling performance with an
analog input as high as 240 MHz.
The AD9244 uses a calibrated 10-stage pipeline architecture
with a patented, wideband, input sample-and-hold amplifier
(SHA) implemented on a cost-effective CMOS process. Each
stage of the pipeline, excluding the last, consists of a low resolu-
tion flash ADC along with a switched capacitor DAC and
interstage residue amplifier (MDAC). The MDAC amplifies the
difference between the reconstructed DAC output and the flash
input for the next stage in the pipeline. One bit of redundancy is
used in each of the stages to facilitate digital correction of flash
errors. The last stage simply consists of a flash ADC.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. While the converter cap-
tures a new input sample every clock cycle, it takes eight clock
cycles for the conversion to be fully processed and appear at the
output, as illustrated in Figure 2. This latency is not a concern
in many applications. The digital output, together with the OTR
indicator, is latched into an output buffer to drive the output
pins. The output drivers of the AD9244 can be configured to
interface with 5 V or 3.3 V logic families.
The AD9244 has a duty clock stabilizer (DCS) that generates its
own internal falling edge to create an internal 50% duty cycle
clock, independent of the externally applied duty cycle. Control
of straight binary or twos complement output format is accom-
plished with the DFS pin.
The ADC samples the analog input on the rising edge of the
clock. While the clock is low, the input SHA is in sample mode.
When the clock transitions to a high logic level, the SHA goes
into the hold mode. System disturbances just prior to or imme-
diately after the rising edge of the clock and/or excessive clock
jitter can cause the SHA to acquire the wrong input value and
should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
The differential input span of the AD9244 is equal to the poten-
tial at the VREF pin. The VREF potential can be obtained from
the internal AD9244 reference or an external source.
In differential applications, the center point of the input span is
the common-mode level of the input signals. In single-ended
applications, the center point is the dc potential applied to one
input pin while the signal is applied to the opposite input pin.
REFT
REFB
VREF
SENSE
AD9244
VIN+
VIN–
33
Ω
20pF
2V
10
μF
0.1
μF
0.1
μF
0.1
μF
0.1
μF
10
μF
33
Ω
50V
REFGND
+
2.5V
1.5V
2.5V
1.5V
02404-040
Figure 40. 2 V p-p Differential Input, Common-Mode Voltage = 2 V
REFT
REFB
VREF
SENSE
AD9244
VIN+
VIN–
33
Ω
20pF
2V
10
μF
0.1
μF
0.1
μF
0.1
μF
0.1
μF
10
μF
33
Ω
REFGND
+
3.0V
2.0V
02404-041
Figure 41. 2 V p-p Single-Ended Input, Common-Mode Voltage = 2 V
REFT
REFB
VREF
SENSE
AD9244
VIN+
VIN–
33
Ω
20pF
0.1pF
2V
2.5V
10
μF
0.1
μF
0.1
μF
0.1
μF
0.1
μF
10
μF
33
Ω
50
Ω
REFGND
+
3.0V
2.0V
3.0V
2.0V
02404-042
Figure 42. 2 V p-p Differential Input, Common-Mode Voltage = 2.5 V
Figure 43 is a simplified model of the AD9244 analog input,
showing the relationship between the analog inputs, VIN+,
VIN–, and the reference voltage, VREF. Note that this is only a
symbolic model and that no actual negative voltages exist inside
the AD9244. Similar to the voltages applied to the top and bot-
tom of the resistor ladder in a flash ADC, the value VREF/2
defines the minimum and maximum input voltages to the
ADC core.
AD9244
+VREF/2
–VREF/2
VIN+
VIN–
VCORE
+
–
ADC
CORE
14
02404-043
Figure 43. Equivalent Analog Input of AD9244
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参数描述 |
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| AD9244BSTZRL-651 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
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| AD9245BCP-20EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9245 3 V A/D Converter,14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
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