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| 型号： | AD9244BSTZRL-65 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SGL 65MSPS 48LQFP |
| 标准包装： | 2,000 |
| 位数： | 14 |
| 采样率（每秒）： | 65M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 550mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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AD9244
Rev. C | Page 24 of 36
Clock Stabilizer (DCS)
The clock stabilizer circuit in the AD9244 desensitizes the ADC
from clock duty cycle variations. System clock constraints are
eased by internally restoring the clock duty cycle to 50%,
independent of the clock input duty cycle. Low jitter on the
rising edge (sampling edge) of the clock is preserved while the
falling edge is generated on-chip.
It may be desirable to disable the clock stabilizer, or necessary
when the clock frequency is varied or completely stopped. Note
that stopping the clock is not recommended with ac-coupled
clocks. Once the clock frequency is changed, more than 100
clock cycles may be required for the clock stabilizer to settle to
the new speed. When the stabilizer is disabled, the internal
switching is directly affected by the clock state. If CLK+ is high,
the SHA is in hold mode; if CLK+ is low, the SHA is in track
mode. Figure 25 shows the benefits of using the clock stabilizer.
Connecting DCS to AVDD implements the internal clock
stabilization function in the AD9244. If the DCS pin is
connected to ground, the AD9244 uses both edges of the
external clock in its internal timing circuitry (see the
Specifications section for timing requirements).
Grounding and Decoupling
Analog and Digital Grounding
Proper grounding is essential in high speed, high resolution
systems. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power distribution.
The use of power and ground planes offers distinct advantages,
including:
The minimization of the loop area encompassed by a signal
and its return path
The minimization of the impedance associated with ground
and power paths
The inherent distributed capacitor formed by the power
plane, PCB material, and ground plane
It is important to design a layout that minimizes noise from
coupling onto the input signal. Digital input signals should not
be run in parallel with input signal traces and should be routed
away from the input circuitry. While the AD9244 features sepa-
rate analog and digital ground pins, it should be treated as an
analog component. The AGND and DGND pins must be joined
together directly under the AD9244. A solid ground plane
under the ADC is acceptable if the power and ground return
currents are carefully managed.
Analog Supply Decoupling
The AD9244 features separate analog and digital supply and
ground circuits, helping to minimize digital corruption of
sensitive analog signals. In general, AVDD (analog power)
should be decoupled to AGND (analog ground). The AVDD
and AGND pins are adjacent to one another. Figure 61 shows
the recommended decoupling for each pair of analog supplies;
0.1 μF ceramic chip and 10 μF tantalum capacitors should pro-
vide adequately low impedance over a wide frequency range.
The decoupling capacitors (especially 0.1 μF) should be located
as close to the pins as possible.
AD9244
AVDD
AGND
10
μF
0.1
μF1
1LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS.
+
02404-061
Figure 61. Analog Supply Decoupling
Digital Supply Decoupling
The digital activity on the AD9244 falls into two categories:
correction logic and output drivers. The internal correction
logic draws relatively small surges of current, mainly during
the clock transitions. The output drivers draw large current
impulses when the output bits change state. The size and
duration of these currents are a function of the load on the
output bits; large capacitive loads should be avoided.
For the digital decoupling shown in Figure 62, 0.1 μF ceramic
chip and 10 μF tantalum capacitors are appropriate. The
decoupling capacitors (especially 0.1 μF) should be located as
close to the pins as possible. Reasonable capacitive loads on the
data pins are less than 20 pF per bit. Applications involving
greater digital loads should consider increasing the digital
decoupling and/or using external buffers/latches.
A complete decoupling scheme also includes large tantalum or
electrolytic capacitors on the power supply connector to reduce
low frequency ripple to insignificant levels.
AD9244
DRVDD
DGND
10
μF
0.1
μF1
1LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS.
+
02404-062
Figure 62. Digital Supply Decoupling
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9244BSTZRL-651 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD9244-EVAL | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 40/65 MSPS Monolithic A/D Converter |
| AD9245 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCP-20EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
| AD9245BCP-20EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9245 3 V A/D Converter,14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
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