- 您现在的位置：买卖IC网 > PDF目录10038 > AD9271BSVZRL-40 (Analog Devices Inc)IC ADC OCT 12BIT 40MSPS 100-TQFP PDF资料下载
参数资料
| 型号： | AD9271BSVZRL-40 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/60页 |
| 文件大小： | 0K |
| 描述： | IC ADC OCT 12BIT 40MSPS 100-TQFP |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 40M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 8 |
| 功率耗散（最大）： | 1.28W |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个差分，单极 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
AD9271
Rev. B | Page 28 of
60
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9271 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 54 shows the preferred method for clocking the AD9271.
A low jitter clock source, such as the Valpey Fisher oscillator
VFAC3-BHL-50MHz, is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9271 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9271, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2812
0.1F
3.3V
50
100
CLK–
CLK+
ADC
AD9271
MINI-CIRCUITS
ADT1-1WT, 1:1Z
XFMR
06
30
4-
05
0
VFAC3
OUT
EN
Figure 54. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 55. The AD951x family of clock drivers offers excellent
jitter performance.
100
0.1F
240
240
AD951x FAMILY
50
*
CLK
*50
RESISTOR IS OPTIONAL.
06304-
051
CLK–
CLK+
ADC
AD9271
PECL DRIVER
3.3V
OUT
VFAC3
EN
100
0.1F
Figure 55. Differential PECL Sample Clock
LVDS DRIVER
CLK
*50
RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9271
06
30
4-
05
2
AD951x FAMILY
3.3V
OUT
VFAC3
EN
50
*
Figure 56. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 57). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1F
39k
CMOS DRIVER
50
*
OPTIONAL
100
0.1F
CLK
*50
RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9271
06
30
4-
05
3
AD951x FAMILY
3.3V
OUT
VFAC3
EN
Figure 57. Single-Ended 1.8 V CMOS Sample Clock
0.1F
CMOS DRIVER
50
*
OPTIONAL
100
CLK
*50
RESISTOR IS OPTIONAL.
0.1F
CLK–
CLK+
ADC
AD9271
06
30
4-
05
4
AD951x FAMILY
3.3V
OUT
VFAC3
EN
Figure 58. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9271 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9271. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]
相关PDF资料 |
PDF描述 |
|---|---|
| MS27474E10B99SC | CONN RCPT 7POS JAM NUT W/SCKT |
| AD1671JQ | IC ADC SNGL 12BIT 28-CDIP |
| VI-BNP-IV-F1 | CONVERTER MOD DC/DC 13.8V 150W |
| VE-J60-MW-B1 | CONVERTER MOD DC/DC 5V 100W |
| AD7878LPZ | IC ADC 12BIT W/DSP INT 28-PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9271BSVZRL-50 | 功能描述:IC ADC OCT 12BIT 50MSPS 100-TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD9271BSVZRL7-25 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9271BSVZRL7-40 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9271BSVZRL7-50 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9272 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
发布紧急采购，3分钟左右您将得到回复。