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| 型号： | AD9271BSVZRL-40 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/60页 |
| 文件大小： | 0K |
| 描述： | IC ADC OCT 12BIT 40MSPS 100-TQFP |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 40M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 8 |
| 功率耗散（最大）： | 1.28W |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个差分，单极 |
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AD9271
Rev. B | Page 33 of
60
When using the serial port interface (SPI), the DCO± phase can
be adjusted in 60° increments relative to the data edge. This
enables the user to refine system timing margins if required.
The default DCO± timing, as shown in Figure 2, is 90° relative
to the output data edge.
An 8-, 10-, and 14-bit serial stream can also be initiated from
the SPI. This allows the user to implement different serial streams
to test the device’s compatibility with lower and higher resolution
systems. When changing the resolution to an 8- or 10-bit serial
stream, the data stream is shortened. When using the 14-bit
option, the data stream stuffs two 0s at the end of the normal
14-bit serial data.
When using the SPI, all of the data outputs can also be inverted
from their nominal state. This is not to be confused with inverting
the serial stream to an LSB-first mode. In default mode, as shown
in Figure 2, the MSB is represented first in the data output serial
stream. However, this can be inverted so that the LSB is repre-
sented first in the data output serial stream (see Figure 3).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This feature is useful when
validating receiver capture and timing. Refer to Table 10 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. It should be noted
that some patterns may not adhere to the data format select
option. In addition, customer user patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode
options except PN sequence short and PN sequence long can
support 8- to 14-bit word lengths in order to verify data capture
to the receiver.
The PN sequence short pattern produces a pseudorandom
bit sequence that repeats itself every 29 1 bits, or 511 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The
only difference is that the starting value is a specific value instead
of all 1s (see Table 11 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 1 bits, or 8,388,607 bits.
A description of the PN sequence and how it is generated can
be found in Section 5.6 of the ITU-T 0.150 (05/96) standard.
The only differences are that the starting value is a specific value
instead of all 1s and the AD9271 inverts the bit stream with
relation to the ITU standard (see Table 11 for the initial values).
Table 11. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short
0x0df
0xdf9, 0x353, 0x301
PN Sequence Long
0x29b80a
0x591, 0xfd7, 0xa3
Consult the Memory Map section for information on how to
change these additional digital output timing features through the
SPI.
SDIO Pin
This pin is required to operate the SPI. It has an internal 30 kΩ
pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
SCLK Pin
This pin is required to operate the SPI port interface. It has an
internal 30 kΩ pull-down resistor that pulls this pin low and is
both 1.8 V and 3.3 V tolerant.
CSB Pin
This pin is required to operate the SPI port interface. It has an
internal 70 kΩ pull-down resistor that pulls this pin low and is
both 1.8 V and 3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
that is nominally equal to 10.0 kΩ between the RBIAS pin and
ground. Using a resistor of another value degrades the performance
of the device. Therefore, it is imperative that at least a 1% tolerance
on this resistor be used to achieve consistent performance.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9271. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input
span of 2.0 V p-p for the ADC. VREF is set internally by default,
but the VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy. However, full-scale ranges below 2.0 V p-p
are not supported by this device.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to reference pins and on the same layer of the
PCB as the AD9271. The recommended capacitor values and
configurations for the AD9271 reference pin can be found in
Table 12. Reference Settings
Selected
Mode
SENSE
Voltage
Resulting
VREF (V)
Resulting
Differential
Span (V p-p)
External
Reference
AVDD
N/A
2 × external
reference
Internal,
2 V p-p FSR
AGND to 0.2 V
1.0
2.0
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相关代理商/技术参数 |
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| AD9271BSVZRL-50 | 功能描述:IC ADC OCT 12BIT 50MSPS 100-TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD9271BSVZRL7-25 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9271BSVZRL7-40 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9271BSVZRL7-50 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9272 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
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