参数资料
型号: AD9271BSVZRL-40
厂商: Analog Devices Inc
文件页数: 26/60页
文件大小: 0K
描述: IC ADC OCT 12BIT 40MSPS 100-TQFP
标准包装: 1,000
位数: 12
采样率(每秒): 40M
数据接口: 串行,SPI?
转换器数目: 8
功率耗散(最大): 1.28W
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-TQFP 裸露焊盘
供应商设备封装: 100-TQFP-EP(14x14)
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极;8 个差分,单极
AD9271
Rev. B | Page 32 of
60
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 9.
To change the output data format to twos complement, see the
Memory Map section.
Table 9. Digital Output Coding
Code
(VIN+) (VIN),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D11 ... D0)
4095
+1.00
1111 1111 1111
2048
0.00
1000 0000 0000
2047
0.000488
0111 1111 1111
0
1.00
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 600 Mbps
(12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See the Memory Map section for details
on enabling this feature.
Two output clocks are provided to assist in capturing data from
the AD9271. DCO± is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9271 and must be captured on the rising and falling edges of
the DCO± that supports double data rate (DDR) capturing. The
frame clock output (FCO±) is used to signal the start of a new
output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
Table 10. Flexible Output Test Modes
Output Test Mode
Bit Sequence
Pattern Name
Digital Output Word 1
Digital Output Word 2
Subject to Data
Format Select
0000
Off (default)
N/A
0001
Midscale short
1000 0000 (8 bits)
10 0000 0000 (10 bits)
1000 0000 0000 (12 bits)
10 0000 0000 0000 (14 bits)
Same
Yes
0010
+Full-scale short
1111 1111 (8 bits)
11 1111 1111 (10 bits)
1111 1111 1111 (12 bits)
11 1111 1111 1111 (14 bits)
Same
Yes
0011
Full-scale short
0000 0000 (8 bits)
00 0000 0000 (10 bits)
0000 0000 0000 (12 bits)
00 0000 0000 0000 (14 bits)
Same
Yes
0100
Checkerboard
1010 1010 (8 bits)
10 1010 1010 (10 bits)
1010 1010 1010 (12 bits)
10 1010 1010 1010 (14 bits)
0101 0101 (8 bits)
01 0101 0101 (10 bits)
0101 0101 0101 (12 bits)
01 0101 0101 0101 (14 bits)
No
0101
PN sequence long1
N/A
Yes
0110
PN sequence short1
N/A
Yes
0111
One-/zero-word toggle
1111 1111 (8 bits)
11 1111 1111 (10 bits)
1111 1111 1111 (12 bits)
11 1111 1111 1111 (14 bits)
0000 0000 (8 bits)
00 0000 0000 (10 bits)
0000 0000 0000 (12 bits)
00 0000 0000 0000 (14 bits)
No
1000
User input
Register 0x19 and Register 0x1A
Register 0x1B and Register 0x1C
No
1001
1-/0-bit toggle
1010 1010 (8 bits)
10 1010 1010 (10 bits)
1010 1010 1010 (12 bits)
10 1010 1010 1010 (14 bits)
N/A
No
1010
1× sync
0000 1111 (8 bits)
00 0001 1111 (10 bits)
0000 0011 1111 (12 bits)
00 0000 0111 1111 (14 bits)
N/A
No
1011
One bit high
1000 0000 (8 bits)
10 0000 0000 (10 bits)
1000 0000 0000 (12 bits)
10 0000 0000 0000 (14 bits)
N/A
No
1100
Mixed bit frequency
1010 0011 (8 bits)
10 0110 0011 (10 bits)
1010 0011 0011 (12 bits)
10 1000 0110 0111 (14 bits)
N/A
No
1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
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