参数资料
| 型号： | AD9518-3ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/64页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
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AD9518-3
Data Sheet
Rev. B | Page 32 of 64
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (Register 0x01D[3]), which causes the holdover
function to always sense LD as high.
If DLD is used, it is possible for the DLD signal to chatter some
while the PLL is reacquiring lock. The holdover function may
retrigger, thereby preventing the holdover mode from ever
terminating. Use of the current source lock detect mode is
recommended to avoid this situation (see the Current Source
Digital Lock Detect section).
Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving the high
impedance state on the reference path PFD event. This helps to
align the edges out of the R and N dividers for faster settling of
the PLL and to reduce frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close because this results in a smaller phase
difference for the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if Register 0x01D[3] = 1) before it can
re-enter holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (Register 0x01C). If the loop loses
lock during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect automatic/internal holdover:
Register 0x018[6:5], lock detect counter. These bits change
the number of consecutive PFD cycles with edges inside the
lock detect window that are required for the DLD indicator
to indicate lock. This impacts the time required before the
LD pin can begin to charge, as well as the delay from the end
of a holdover event until the holdover function can be
re-engaged.
Register 0x018[3], disable digital lock detect. This bit must be
set to 0b to enable the DLD circuit. Automatic/internal hold-
over does not operate correctly without the DLD function
enabled.
Register 0x01A[5:0], lock detect pin output select. Set these
bits to 000100b for the current source lock detect mode
if using the LD pin comparator. Load the LD pin with
a capacitor of an appropriate value.
Register 0x01D[3], enable LD pin comparator. 1 = enable;
0 = disable. When disabled, the holdover function always
senses the LD pin as high.
Register 0x01D[1], enable external holdover control.
Register 0x01D[0] and Register 0x01D[2], enable holdover
function. If holdover is disabled, both external and
automatic/internal holdover are disabled.
For example, to use automatic holdover with the following:
Automatic reference switchover, prefer REF1
Digital lock detect: five PFD cycles, high range window
Automatic holdover using the LD pin comparator
Set the following registers (in addition to the normal PLL registers):
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; lock detect window = high range.
Register 0x018[3] = 0b; DLD normal operation.
Register 0x01A[5:0] = 000100b; current source lock detect
mode.
Register 0x01B[7:0] = 0xF7; set REFMON pin to status of
REF1 (active low).
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[2]=1b; enable the holdover function.
Register 0x01D[1] = 0b; use internal/automatic holdover
mode.
Register 0x01D[0] = 1b; enable the holdover function.
(VCO calibration must be complete before this bit is
enabled.)
Connect REFMON pin to REFSEL pin.
Frequency Status Monitors
The AD9518 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is shown
in Figure 39. The VCO status frequency monitor is also capable
of monitoring the CLK input if the CLK input is selected as the
input to the N divider.
The PLL reference frequency monitors have two threshold
frequencies: normal and extended (see Table 15). The reference
frequency monitor thresholds are selected in Register 0x01A
The frequency monitor status can be found in Register 0x01F,
Bits[3:1].
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相关代理商/技术参数 |
参数描述 |
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| AD9518-3ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 2GHZ 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9518-3A-PCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:6-Output Clock Generator with 6-Output Clock Generator with |
| AD9518-3BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9518-3BCPZ-REEL7 | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP T/R |
| AD9518-4 | 制造商:AD 制造商全称:Analog Devices 功能描述:6-Output Clock Generator with Integrated 1.6 GHz VCO |
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