参数资料
| 型号： | AD9518-3ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/64页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
Data Sheet
AD9518-3
Rev. B | Page 37 of 64
Synchronizing the Outputs—Sync Function
The most common way to execute the sync function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low-going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The
timing of the sync operation is shown in
(using the
VCO divider) and
(VCO divider not used). There is
an uncertainty of up to one cycle of the clock at the input to the
channel divider due to the asynchronous nature of the SYNC
signal with respect to the clock edges inside the
. The
delay from the
SYNC rising edge to the beginning of synchronized
output clocking is between 14 and 15 cycles of clock at the channel
divider input, plus either one cycle of the VCO divider input
(see
), or one cycle of the channel divider input (see
), depending on whether the VCO divider is used.
Cycles are counted from the rising edge of the signal.
The AD9518 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and subsequently releasing these
outputs to continue clocking at the same instant with the preset
conditions applied. This allows for the alignment of the edges of
two or more outputs or for the spacing of edges according to the
coarse phase offset settings for two or more outputs.
Output synchronization is executed in several ways, as follows:
By forcing the SYNC pin low, then releasing it (manual sync).
By setting, then resetting, any one of the following three bits:
the soft sync bit (Register 0x230[0]), the soft reset bit
(Register 0x000[2] [mirrored]), and the power-down
distribution reference bit (Register 0x230[1]).
Another common way to execute the sync function is by setting
and resetting the soft sync bit at Register 0x230[0] (see Table 43
through Table 49 for details). Both the setting and resetting
of the soft sync bit require an update all registers operation
(Register 0x232[0] = 1) to take effect.
By executing synchronization of the outputs as part of the
chip power-up sequence.
By forcing the RESET pin low, then releasing it (chip reset).
By forcing the PD pin low, then releasing (chip power-down).
Following completion of a VCO calibration. An internal
SYNC signal is automatically asserted at the beginning of
a VCO calibration, then released upon its completion.
1
2
34
56
7
8
910
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
1
11
12
13
14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
06
432
-0
73
Figure 41. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
INPUT TO CLK
IINPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
12
3
4
5
6
7
8
910
11
12
13
14
1
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
0
643
2-
07
4
Figure 42. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
相关PDF资料 |
PDF描述 |
|---|---|
| AD9518-4ABCPZ-RL7 | IC CLOCK GEN 6CH 1.8GHZ 48LFCSP |
| AD9520-0BCPZ-REEL7 | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| AD9520-1BCPZ | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| AD9520-2BCPZ | IC CLOCK GEN 2.2GHZ VCO 64LFCSP |
| AD9520-3BCPZ-REEL7 | IC CLOCK GEN 2GHZ VCO 64LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9518-3ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 2GHZ 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9518-3A-PCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:6-Output Clock Generator with 6-Output Clock Generator with |
| AD9518-3BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9518-3BCPZ-REEL7 | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP T/R |
| AD9518-4 | 制造商:AD 制造商全称:Analog Devices 功能描述:6-Output Clock Generator with Integrated 1.6 GHz VCO |
发布紧急采购，3分钟左右您将得到回复。