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| 型号： | AD9522-0BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/84页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.95GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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AD9522-0
Rev. 0 | Page 34 of 84
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs and
tells the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the internal VCO through the LF pin (or the
tuning pin of an external VCO) to move the VCO frequency up
or down. The CP can be set (0x010[3:2]) for high impedance
(allows holdover operation), for normal operation (attempts to
lock the PLL loop), for pump-up, or for pump-down (test modes).
The CP current is programmable in eight steps from (nominally)
0.6 mA to 4.8 mA. The exact value of the CP current LSB is set
by the CPRSET resistor, which is nominally 5.1 kΩ.
On-Chip VCO
The AD9522 includes an on-chip VCO covering the frequency
range shown in Table 2. Achieving low VCO phase noise was a
priority in the design of the VCO.
To tune over the wide range of frequencies covered by this
VCO, tuning ranges are used. The calibration procedure selects
the correct range for the desired VCO frequency. See the VCO
Calibration section for additional information.
The on-chip VCO is powered by an on-chip, low dropout (LDO),
linear voltage regulator. The LDO provides some isolation of
the VCO from variations in the power supply voltage level.
The BYPASS pin should be connected to ground by a 220 nF
capacitor to ensure stability. This LDO employs the same
technology used in the anyCAP line of regulators from Analog
Devices, Inc., making it insensitive to the type of capacitor used.
Driving an external load from the BYPASS pin is not supported.
When an external VCO/VCXO is use, the BYPASS and LF pins
should be left floating. This configuration is shown in Figure 42.
PLL External Loop Filter
When an internal VCO is used, the external loop filter should
be referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for a PLL
that uses the internal VCO is shown in Figure 41. A loop filter
must be calculated for each desired PLL configuration. The values
of the components depend upon the VCO frequency, the KVCO,
the PFD frequency, the CP current, the desired loop bandwidth,
and the desired phase margin. The loop filter affects the phase
noise, the loop settling time, and the loop stability. A basic
knowledge of PLL theory is helpful for understanding loop filter
design. ADIsimCLK can help with the calculation of a loop
filter according to the application requirements.
When an external VCO is used, the external loop filter should
be referenced to ground. An example of an external loop filter
for a PLL using an external VCO is shown in Figure 42.
LF
VCO
CHARGE
PUMP
CP
BYPASS
C1
C2
C3
R1
R2
CBP = 220nF
AD9522
0
72
19
-06
5
Figure 41. Example of External Loop Filter for a PLL Using the Internal VCO
CLK/CLK
EXTERNAL
VCO/VCXO
CHARGE
PUMP
CP
C1
C2
C3
R1
R2
AD9522
072
19
-26
5
Figure 42. Example of External Loop Filter for a PLL Using an External VCO
PLL Reference Inputs
The AD9522 features a flexible PLL reference input circuit that
allows a fully differential input, two separate single-ended inputs,
or a 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip
maintaining amplifier. An optional reference clock doubler
can be used to double the PLL reference frequency. The input
frequency range for the reference inputs is specified in Table 2.
Both the differential and the single-ended inputs are self-biased,
allowing for easy ac coupling of input signals.
Either a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential input and the single-ended inputs share two pins,
REFIN (REF1) and REFIN (REF2). The desired reference input
type is selected and controlled by 0x01C (see
and
).
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly to prevent chattering of
the input buffer when the reference is slow or missing. The
specification for this voltage level can be found in Table 2.
The input hysteresis increases the voltage swing required of
the driver to overcome the offset.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
To avoid input buffer chatter when a single-ended, ac-coupled
input signal stops toggling, the user can set 0x018[7] to 1b. This
shifts the dc offset bias point down 140 mV. To increase isolation
and reduce power, each single-ended input can be independently
powered down.
The differential reference input receiver is powered down when
it is not selected or when the PLL is powered down. The single-
ended buffers power down when the PLL is powered down or
when their respective individual power-down registers are set.
When the differential mode is selected, the single-ended inputs
are powered down.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9522-1 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 2.4 GHz VCO |
| AD9522-1/PCBZ | 功能描述:BOARD EVAL FOR AD9522-1 CLK GEN RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9522-1BCPZ | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| AD9522-1BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9522-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
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