- 您现在的位置：买卖IC网 > PDF目录1987 > AD9522-1BCPZ-REEL7 (Analog Devices Inc)IC CLOCK GEN 2.5GHZ VCO 64LFCSP PDF资料下载
参数资料
| 型号： | AD9522-1BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 74/84页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页当前第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页
AD9522-1
Rev. 0 | Page 76 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
192
[2]
Channel 0 power-down
Channel 0 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into the high
impedance power-down mode by setting this bit.)
192
[0]
Disable Divider 0 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
193
[7:4]
Divider 1 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x3 means the divider is low for four input clock cycles (default: 0x3).
193
[3:0]
Divider 1 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x3 means the divider is high for four input clock cycles (default: 0x3).
194
[7]
Divider 1 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
194
[6]
Divider 1 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
194
[5]
Divider 1 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
194
[4]
Divider 1 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
194
[3:0]
Divider 1 phase offset
Phase offset (default: 0x0).
195
[2]
Channel 1 power-down
Channel 1 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into the high
impedance power-down mode by setting this bit.)
195
[0]
Disable Divider 1 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
196
[7:4]
Divider 2 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x1 means the divider is low for two input clock cycles (default: 0x1).
196
[3:0]
Divider 2 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1).
197
[7]
Divider 2 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
197
[6]
Divider 2 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
197
[5]
Divider 2 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
197
[4]
Divider 2 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
197
[3:0]
Divider 2 phase offset
Phase offset (default: 0x0).
相关PDF资料 |
PDF描述 |
|---|---|
| AD9522-2BCPZ | IC CLOCK GEN 2.2GHZ VCO 64LFCSP |
| AD9522-3BCPZ-REEL7 | IC CLOCK GEN 2GHZ VCO 64LFCSP |
| AD9522-4BCPZ-REEL7 | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| AD9522-5BCPZ | IC CLOCK GEN 2.4GHZ 64LFCSP |
| AD9523-1BCPZ-REEL7 | IC INTEGER-N CLCK GEN 72LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9522-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
| AD9522-2/PCBZ | 功能描述:BOARD EVAL FOR AD9522-2 CLK GEN RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9522-2BCPZ | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9522-2BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9522-3 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 2 GHz VCO |
发布紧急采购，3分钟左右您将得到回复。