参数资料
| 型号： | AD9524BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/56页 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N CLCK GEN 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，扇出缓冲器（分配） |
| PLL： | 是 |
| 主要目的： | 以太网，光纤通道，SONET/SDH |
| 输入： | CMOS |
| 输出： | HSTL，LVCMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 相关产品： | AD9524BCPZ-REEL7DKR-ND - IC INTEGER-N CLCK GEN 48LFCSP AD9524BCPZ-REEL7CT-ND - IC INTEGER-N CLCK GEN 48LFCSP AD9524/PCBZ-ND - BOARD EVAL FOR AD9524 AD9524BCPZ-REEL7TR-ND - IC INTEGER-N CLCK GEN 48LFCSP |
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AD9524
Data Sheet
Rev. E | Page 18 of 56
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in decibels) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of ADCs,
DACs, and RF mixers. It lowers the achievable dynamic range of
the converters and mixers, although they are affected in somewhat
different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in seconds root
mean square (rms) or 1 sigma (Σ) of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that can be
attributed to the device or subsystem being measured. The phase
noise of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system phase noise when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own phase noise to the total. In many cases, the
phase noise of one element dominates the system phase noise.
When there are multiple contributors to phase noise, the total
is the square root of the sum of squares of the individual
contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that can be
attributed to the device or subsystem being measured. The time
jitter of any external oscillators or clock sources is subtracted. This
makes it possible to predict the degree to which the device impacts
the total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contributes
its own time jitter to the total. In many cases, the time jitter of the
external oscillators and clock sources dominates the system
time jitter.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9524BCPZ-REEL7 | 功能描述:IC INTEGER-N CLCK GEN 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| AD9525 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Jitter Clock Generator with Eight LVPECL Outputs |
| AD9525/PCBZ | 功能描述:时钟和定时器开发工具 Evaluation kit 2950MHz VCO installed RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| AD9525/PCBZ-VCO | 功能描述:时钟和定时器开发工具 Evaluation kit CRO29508 VCO installed RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| AD9525BCPZ | 功能描述:时钟发生器及支持产品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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