参数资料
| 型号： | AD9524BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/56页 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N CLCK GEN 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，扇出缓冲器（分配） |
| PLL： | 是 |
| 主要目的： | 以太网，光纤通道，SONET/SDH |
| 输入： | CMOS |
| 输出： | HSTL，LVCMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 相关产品： | AD9524BCPZ-REEL7DKR-ND - IC INTEGER-N CLCK GEN 48LFCSP AD9524BCPZ-REEL7CT-ND - IC INTEGER-N CLCK GEN 48LFCSP AD9524/PCBZ-ND - BOARD EVAL FOR AD9524 AD9524BCPZ-REEL7TR-ND - IC INTEGER-N CLCK GEN 48LFCSP |
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AD9524
Data Sheet
Rev. E | Page 14 of 56
Pin
No.
Mnemonic
Type1
Description
This pin has an internal 40 k pull-down resistor in SPI mode but is high impedance in IC mode.
17
SDIO/SDA
I/O
Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or IC Mode (SDA).
18
SDO
O
Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode).
There is no internal pull-up/pull-down resistor on this pin.
19
OUT5
O
Complementary Clock Output 5. This pin can be configured as one side of a differential
LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
20
OUT5
O
Clock Output 5. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a
single-ended CMOS output.
21
VDD3_OUT[4:5]
P
3.3 V Supply for Output 4 and Output 5 Clock Drivers.
22
OUT4
O
Complementary Clock Output 4. This pin can be configured as one side of a differential
LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
23
OUT4
O
Clock Output 4. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a
single-ended CMOS output.
24
VDD1.8_OUT[4:5]
P
1.8 V Supply for Output 4 and Output 5 Clock Dividers.
25
REF_TEST
I
Test Input to PLL1 Phase Detector.
26
RESET
I
Digital Input, Active Low. Resets internal logic to default states. This pin has an internal
40 k pull-up resistor.
27
PD
Chip Power-Down, Active Low. This pin has an internal 40 k pull-up resistor.
28
EEPROM_SEL
I
EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to
be loaded at reset and/or power-up. Setting this pin low causes the
AD9524 to load the hard-
coded default register values at power-up/reset. This pin has an internal 40 k pull-down resistor.
29
OUT3
O
Complementary Clock Output 3. This pin can be configured as one side of a differential
LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
30
OUT3
O
Square Wave Clocking Output 3. This pin can be configured as one side of a differential
LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
31
VDD3_OUT[2:3]
P
3.3 V Supply Output 2 and Supply Output 3 Clock Drivers.
32
OUT2
O
Complementary Clock Output 2. This pin can be configured as one side of a differential
LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
33
OUT2
O
Clock Output 2. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a
single-ended CMOS output.
34
VDD1.8_OUT[2:3]
P
1.8 V Supply for Output 2 and Output 3 Clock Dividers.
35
STATUS1/SP1
I/O
Lock Detect and Other Status Signals (STATUS1)/I2C Address (SP1).
36
STATUS0/SP0
I/O
Lock Detect and Other Status Signals (STATUS0)/I2C Address (SP0).
37
OUT1
O
Complementary Clock Output 1. This pin can be configured as one side of a differential
LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
38
OUT1
O
Clock Output 1. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a
single-ended CMOS output.
39
VDD3_OUT[0:1]
P
3.3 V Supply Output 0 and Supply Output 1 Clock Drivers.
40
OUT0
O
Complementary Clock Output 0. This pin can be configured as one side of a differential
LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
41
OUT0
O
Clock Output 0. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a
single-ended CMOS output.
42
VDD1.8_OUT[0:1]
P
1.8 V Supply for Output 0 and Output 1 Clock Dividers.
43
ZD_IN
I
External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
44
ZD_IN
I
Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input
for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
45
REF_SEL
I
Reference Input Select. This pin has an internal 40 k pull-down resistor.
46
PLL1_OUT
O
Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in
Register 0x1BA, Bit 4 (see Table 53).
47
LDO_PLL1
P/O
1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 F decoupling capacitor
from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be
placed in close proximity to the device.
48
VDD3_PLL1
P
3.3 V Supply PLL1. Use the same supply as VCXO.
EP
EP, GND
GND
Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered
to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and
mechanical strength benefits.
1
P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground.
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| AD9524BCPZ-REEL7 | 功能描述:IC INTEGER-N CLCK GEN 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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| AD9525/PCBZ-VCO | 功能描述:时钟和定时器开发工具 Evaluation kit CRO29508 VCO installed RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| AD9525BCPZ | 功能描述:时钟发生器及支持产品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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