参数资料
型号: AD9540BCPZ
厂商: Analog Devices Inc
文件页数: 1/32页
文件大小: 0K
描述: IC CLOCK GENERATOR PLL 48-LFCSP
标准包装: 1
类型: 时钟发生器
PLL:
输入: 时钟
输出: CML,PECL
电路数: 1
比率 - 输入:输出: 2:2
差分 - 输入:输出: 是/是
频率 - 最大: 655MHz
除法器/乘法器: 是/无
电源电压: 1.71 V ~ 1.89 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 托盘
产品目录页面: 776 (CN2011-ZH PDF)
655 MHz Low Jitter Clock Generator
AD9540
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
Excellent intrinsic jitter performance
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 programmable phase/frequency profiles
400 MSPS internal DDS clock speed
48-bit frequency tuning word resolution
14-bit programmable phase offset
1.8 V supply for device operation
3.3 V supply for I/O, CML driver, and charge pump output
Software controlled power-down
48-lead LFCSP_VQ package
Programmable charge pump current (up to 4 mA)
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant output driver
APPLICATIONS
Clocking high performance data converters
Base station clocking applications
Network (SONET/SDH) clocking
Gigabit Ethernet (GbE) clocking
Instrumentation clocking circuits
Agile LO frequency synthesis
Automotive radar
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND
CP_VDD
CP_RSET
CP
REF, AMP
REFIN
CLK1
CHARGE
PUMP
PHASE
FREQUENCY
DETECTOR
M DIVIDER
N DIVIDER
DIVIDER
1, 2, 4, 8
SYNC_IN/STATUS
SYNC, PLL
LOCK
SCLK
SDI/O
SDO
CS
SERIAL
CONTROL
PORT
TIMING AND
CONTROL LOGIC
CLK2
CP_OUT
CLK2
DRV_RSET
OUT0
CML
OUT0
CLK
DIVCLK
S2
S1
S0
PHASE/
FREQUENCY
PROFILES
DDS
IOUT
DAC
DAC_RSET
48
10
14
04947-001
AD9540
Figure 1.
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