参数资料
| 型号： | AD9540BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/32页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GENERATOR PLL 48-LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML，PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 655MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
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AD9540
Rev. A | Page 20 of 32
DDS AND DAC
Finally, the amplitude words are piped to a 10-bit DAC. Because
the DAC is a sampled data system, the output is a reconstructed
sine wave that needs to be filtered to take high frequency images
out of the spectrum. The DAC is a current steering DAC that is
AVDD referenced. To get a measurable voltage output, the DAC
outputs must be terminated through a load resistor to AVDD,
typically 50 . At positive full scale, IOUT sinks no current and
the voltage drop across the load resistor is 0. However, the IOUT
output sinks the programmed full-scale output current of the
DAC, causing the maximum output voltage drop across the load
resistor. At negative full-scale, the situation is reversed and IOUT
sinks the full-scale current (and generates the maximum drop
across the load resistor), while IOUT sinks no current (and
generates no voltage drop). At midscale, the outputs sink equal
amounts of current, generating equal voltage drops.
The precision frequency division within the device is
accomplished using DDS technology. The DDS can control the
digital phase relationships by clocking a 48-bit accumulator.
The incremental value loaded into the accumulator, known as
the frequency tuning word, controls the overflow rate of the
accumulator. Similar to a sine wave completing a 2π radian
revolution, the overflow of the accumulator is cyclical in nature
and generates a fundamental frequency according to
48
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( s
o
f
FTW
f
×
=
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2
W
{0
47
≤
≤ FT
The instantaneous phase of the sine wave is therefore the output
of the phase accumulator block. This signal can be phase-offset
by programming an additive digital phase that is added to each
phase sample coming out of the accumulator.
These instantaneous phase values are then piped through a
phase-to-amplitude conversion (sometimes called an angle-to-
amplitude conversion or AAC) block. This algorithm follows a
COS(x) relationship, where x is the phase coming out of the
phase offset block, normalized to 2π.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9540BCPZ-REEL | 制造商:AD 制造商全称:Analog Devices 功能描述:655 MHz Low Jitter Clock Generator |
| AD9540BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNTHESIZER 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9540PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:655 MHz Low Jitter Clock Generator |
| AD9540-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9540 ,655 MHZ LOW JITTER CLOCK GEN - Trays |
| AD9540-VCO/PCBZ | 功能描述:BOARD EVAL CLK GEN SYNTH 48LFCSP RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
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