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| 型号： | AD9640ABCPZ-105 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/52页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 105MSPS 64LFCSP |
| 设计资源： | Interfacing ADL5534 to AD9640 High Speed ADC (CN0049) |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 105M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 657mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极 |
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AD9640
Rev. B | Page 35 of 52
SIGNAL MONITOR
The signal monitor block provides additional information
about the signal being digitized by the ADC. The signal monitor
computes the rms input magnitude, the peak magnitude,
and/or the number of samples by which the magnitude exceeds
a particular threshold. Together, these functions can be used to
gain insight into the signal characteristics and to estimate the
peak/average ratio or even the shape of the complementary cumu-
lative distribution function (CCDF) curve of the input signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
The signal monitor result values can be obtained from the part by
reading back internal registers at Address 0x116 to Address 0x11B,
using the SPI port or the signal monitor SPORT output. The output
contents of the SPI-accessible signal monitor registers are set via
the two signal monitor mode bits of the signal monitor control
register. Both ADC channels must be configured for the same
signal monitor mode (Address 0x112). Separate SPI-accessible,
20-bit signal monitor result (SMR) registers are provided for each
ADC channel. Any combination of the signal monitor functions
can also be output to the user via the serial SPORT interface.
These outputs are enabled using the peak detector output enable
bit, the rms/ms magnitude output enable bit, and the threshold
crossing output enable bit in the signal monitor SPORT control
register.
For each signal monitor measurement, a programmable signal
monitor period register (SMPR) controls the duration of the
measurement. This period of time is programmed as the number
of input clock cycles in a 24-bit signal monitor period register
located at Address 0x113, Address 0x114, and Address 0x115.
This register can be programmed with a period from 128 samples
to 16.78 (224) million samples.
Because the dc offset of the ADC can be significantly larger
than the signal of interest (affecting the results from the signal
monitor), a dc correction circuit is included as part of the signal
monitor block to null the dc offset before measuring the power.
PEAK DETECTOR MODE
The magnitude of the input port signal is monitored over a
programmable time period (determined by the SMPR) to give
the peak value detected. This function is enabled by programming
a Logic 1 in the signal monitor mode bits of the signal monitor
control register or by setting the peak detector output enable bit
in the signal monitor SPORT control register. The 24-bit SMPR
must be programmed before activating this mode.
After enabling this mode, the value in the SMPR is loaded into
a monitor period timer, and the countdown is started. The magni-
tude of the input signal is compared with the value in the internal
peak level holding register (not accessible to the user), and the
greater of the two is updated as the current peak level. The initial
value of the peak level holding register is set to the current ADC
input signal magnitude. This comparison continues until the
monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding register
(not accessible to the user), which can be read through the SPI port
or output through the SPORT serial interface. The monitor period
timer is reloaded with the value in the SMPR, and the countdown is
restarted. In addition, the magnitude of the first input sample is
updated in the peak level holding register, and the comparison and
update procedure, as explained previously, continues.
Figure 68 is a block diagram of the peak detector logic. The SMR
register contains the absolute magnitude of the peak detected by
the peak detector logic.
SIGNAL MONITOR
HOLDING
REGISTER (SMR)
MAGNITUDE
STORAGE
REGISTER
COMPARE
A>B
TO
MEMORY
MAP/SPORT
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
LOAD
IS COUNT = 1?
DOWN
COUNTER
SIGNAL MONITOR
PERIOD REGISTER
06
54
7-
0
44
Figure 68. ADC Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE
In this mode, the root-mean-square (rms) or mean-square (ms)
magnitude of the input port signal is integrated (by adding an
accumulator) over a programmable period of time (determined by
the SMPR) to give the rms or ms magnitude of the input signal.
This mode is set by programming Logic 0 in the signal monitor
mode bits of the signal monitor control register or by setting the
rms/ms magnitude output enable bit in the signal monitor SPORT
control register. The 24-bit SMPR, representing the period over
which integration is performed, must be programmed before acti-
vating this mode.
After enabling the rms/ms magnitude mode, the value in the SMPR
is loaded into a monitor period timer, and the countdown is started
immediately. Each input sample is converted to floating-point
format and squared. It is then converted to 11-bit, fixed-point
format and added to the contents of the 24-bit accumulator.
The integration continues until the monitor period timer reaches
a count of 1.
When the monitor period timer reaches a count of 1, the square
root of the value in the accumulator is taken and transferred,
after some formatting, to the signal monitor holding register, which
can be read through the SPI port or output through the SPORT
serial port. The monitor period timer is reloaded with the value
in the SMPR, and the countdown is restarted. In addition, the
first input sample signal power is updated in the accumulator,
and the accumulation continues with the subsequent input
samples.
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