参数资料
型号: AD9726BSVZ
厂商: Analog Devices Inc
文件页数: 8/24页
文件大小: 0K
描述: IC DAC 16IT LVDS 400MSPS 80-TQFP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1
系列: TxDAC+®
位数: 16
数据接口: 并联
转换器数目: 1
电压电源: 模拟和数字
功率耗散(最大): 575mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 80-TQFP 裸露焊盘
供应商设备封装: 80-TQFP-EP(12x12)
包装: 托盘
输出数目和类型: 2 电流,单极
采样率(每秒): 400M
产品目录页面: 785 (CN2011-ZH PDF)
配用: AD9726-EBZ-ND - BOARD EVAL FOR AD9726
AD9726
Rev. B | Page 16 of 24
Addr
Name
Bits
I/O
Default
Description
0x10
MEMADR
[7:0]
I
00000000
8-bit memory address value for read/write operations.
0x11
MEMDAT
[5:0]
I/O
000000
6-bit memory data value for read/write operations.
0x15
SYNCOUT
[1:0]
O
00
2-bit output value indicates current sync quadrant.
0x16
BYPASS
6
I
0
1: bypasses data synchronization circuitry. Data is sampled using the DAC clock (CLK±)
SYNCEXT
5
I
0
1: enables sync external mode; disable auto quadrant select.
SYNCIN
[4:3]
I
00
2-bit input value is used to specify the sync quadrant.
1 SWRESET also resets itself. SMEM contents are unaffected by SWRESET; however, CALMEM reports an uncalibrated state.
2 EXTREF is optional because the internal reference circuit is designed to be overdriven by an external source.
3 The self-calibration clock is also used for the memory transfer cycle; therefore, the CALCLK value affects the MEMXFER process time.
4 Register Bits 3:0 must all be 0 to assert SELFCAL. The time required for the self-calibration cycle is ~100 ms at 100 MHz with CALCLK = 0.
5 Register Bits 3:0 must all be 0 to assert MEMXFER. The time required for the memory transfer cycle is ~15 ms at 100 MHz with CALCLK = 0.
6 The UNCAL bit remains asserted after the cycle completes (SMEM contents held at default values) until the bit is cleared by the user.
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