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型号： AD9883ABSTZ-RL110
厂商： Analog Devices Inc
文件页数： 11/28页
文件大小： 0K
描述： IC INTERFACE FLAT 110MHZ 80LQFP
标准包装： 1
应用： 显示器，监控器，电视
接口： 模拟
电源电压： 3 V ~ 3.6 V
封装/外壳： 80-LQFP
供应商设备封装： 80-LQFP（14x14）
包装： 标准包装
安装类型： 表面贴装
其它名称： AD9883ABSTZ-RL110DKR
REV. B
AD9883A
–19–
0E
5
Hsync Output Polarity
This bit determines the polarity of the Hsync output and
the SOG output. Table XI shows the effect of this option.
SYNC indicates the logic state of the sync pulse.
Table XI. Hsync Output Polarity Settings
Setting
SYNC
0Logic 1 (Positive Polarity)
1Logic 0 (Negative Polarity)
The default setting for this register is 0.
0E
4
Active Hsync Override
This bit is used to override the automatic Hsync selection,
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
Table XII. Active Hsync Override Settings
Override
Result
0Autodetermines the Active Interface
1
Override, Bit 3 Determines the Active Interface
The default for this register is 0.
0E
3
Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 4). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
Table XIII. Active HSYNC Select Settings
Select
Result
0HSYNC Input
1
Sync-on-Green Input
The default for this register is 0.
0E
2
Vsync Output Invert
This bit inverts the polarity of the Vsync output. Table
XIV shows the effect of this option.
Table XIV. Vsync Output Invert Settings
Setting
Vsync Output
0
Invert
1No Invert
The default setting for this register is 0.
0E
1 Active Vsync Override
This bit is used to override the automatic Vsync selection.
To override, set this bit to Logic 1. When overriding, the
active interface is set via Bit 0 in this register.
Table XV. Active Vsync Override Settings
Override
Result
0Autodetermine the Active Vsync
1
Override, Bit 0 Determines the Active Vsync
The default for this register is 0.
0E
0 Active Vsync Select
This bit is used to select the active Vsync when the over-
ride bit is set (Bit 1).
Table XVI. Active Vsync Select Settings
Select
Result
0Vsync Input
1Sync Separator Output
The default for this register is 0.
0F
7 Clamp Input Signal Source
This bit determines the source of clamp timing.
Table XVII. Clamp Input Signal Source Settings
Clamp Function
Function
0Internally Generated Clamp Signal
1
Externally Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the leading edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is active.
The polarity of CLAMP is determined by the Clamp
Polarity bit (Register 0FH, Bit 6).
The power-up default value is Clamp Function = 0.
0F
6 Clamp Input Signal Polarity
This bit determines the polarity of the externally provided
CLAMP signal.
Table XVIII. Clamp Input Signal Polarity Settings
Clamp Function
Function
1Active Low
0Active High
A Logic 1 means that the circuit will clamp when CLAMP is
low, and it will pass the signal to the ADC when CLAMP is
high.
A Logic 0 means that the circuit will clamp when CLAMP
is high, and it will pass the signal to the ADC when
CLAMP is low.
The power-up default value is Clamp Polarity = 1.
0F
5 Coast Select
This bit is used to select the active Coast source. The
choices are the Coast Input Pin or Vsync. If Vsync is se-
lected the additional decision of using the Vsync input
pin or the output from the sync separator needs to be
made (Register 0E, Bits 1, 0).
Table XIX. Power-Down Settings
Select
Result
0Coast Input Pin
1Vsync (See above Text)
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