参数资料
| 型号： | AD9949KCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/36页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| 标准包装： | 1 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
AD9949
Rev. B | Page 21 of 36
HORIZONTAL CLAMPING AND BLANKING
The AD9949’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual
sequences are defined for each signal, which are then organized
into multiple regions during image readout. This allows the
dark pixel clamping and blanking patterns to be changed at
each stage of the readout to accommodate different image
transfer timing and high speed line shifts.
INDIVIDUAL CLPOB AND PBLK SEQUENCES
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 21. These two signals are independently
programmed using the parameters shown in Table 18. The start
polarity, first toggle position, and second toggle position are
fully programmable for each signal. The CLPOB and PBLK
signals are active low and should be programmed accordingly.
Up to four individual sequences can be created for each signal.
INDIVIDUAL HBLK SEQUENCES
The HBLK programmable timing shown in Figure 22 is similar
to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the
start and the stop positions of the blanking period. Additionally,
there is a polarity control, HBLKMASK, which designates the
polarity of the horizontal clock signals H1 to H4 during the
blanking period. Setting HBLKMASK high sets H1 = H3 = low
and H2 = H4 = high during the blanking, as shown in Figure 23.
Up to four individual sequences are available for HBLK.
3
2
1
HD
CLPOB
PBLK
PROGRAMMABLE SETTINGS:
1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
2. FIRST TOGGLE POSITION.
3. SECOND TOGGLE POSITION.
ACTIVE
03751-022
...
Figure 21. Clamp and Preblank Pulse Placement
2
1
HD
HBLK
PROGRAMMABLE SETTINGS:
1. FIRST TOGGLE POSITION = START OF BLANKING.
2. SECOND TOGGLE POSITION = END OF BLANKING.
BLANK
03751-023
...
Figure 22. Horizontal Blanking (HBLK) Pulse Placement
Table 18. CLPOB and PBLK Individual Sequence Parameters
Parameter
Length
Range
Description
Polarity
1b
High/Low
Starting Polarity of Clamp and PBLK Pulses for Sequences 0 to 3
.
Toggle Position 1
12b
0 to 4095 Pixel Location
First Toggle Position within the Line for Sequences 0 to 3
.
Toggle Position 2
12b
0 to 4095 Pixel Location
Second Toggle Position within the Line for Sequences 0 to 3
.
Table 19. HBLK Individual Sequence Parameters
Parameter
Length
Range
Description
HBLKMASK
1b
High/Low
Masking Polarity for H1 for Sequences 0 to 3 (0 = H1 Low, 1 = H1 High).
Toggle Position 1
12b
0 to 4095 Pixel Location
First Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 2
12b
0 to 4095 Pixel Location
Second Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 3
12b
0 to 4095 Pixel Location
Third Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 4
12b
0 to 4095 Pixel Location
Fourth Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 5
12b
0 to 4095 Pixel Location
Fifth Toggle Position within the Line for Sequences 0 to 3.
Toggle Position 6
12b
0 to 4095 Pixel Location
Sixth Toggle Position within the Line for Sequences 0 to 3.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9951YSVZ | IC DDS DAC 14BIT 1.8V 48-TQFP |
| AD9952YSVZ-REEL7 | IC DDS DAC 14BIT 1.8V 48TQFP |
| AD9953YSVZ-REEL7 | IC DDS DAC 14BIT 1.8V 48TQFP |
| AD9954YSVZ-REEL7 | IC DDS DAC 14BIT 1.8V 48TQFP |
| AD9956YCPZ-REEL7 | IC SYNTHESIZER 1.8V 48LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9949KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 40-LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 传感器和探测器接口 系列:- 其它有关文件:Automotive Product Guide 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:74 系列:- 类型:触控式传感器 输入类型:数字 输出类型:数字 接口:JTAG，串行 电流 - 电源:100µA 安装类型:表面贴装 封装/外壳:20-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:20-TSSOP 包装:管件 |
| AD9950KJ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Parallel-Input Frequency Synthesizer |
| AD9950TJ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Parallel-Input Frequency Synthesizer |
| AD9951 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9951/PCBZ | 制造商:Analog Devices 功能描述:AD9951 400 MSPS DDS W/ 14 BIT DAC EVALBD - Boxed Product (Development Kits) |
发布紧急采购，3分钟左右您将得到回复。