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参数资料
| 型号： | AD9957BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/64页 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1,000 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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AD9957
Data Sheet
Rev. C | Page 36 of 64
PLL CHARGE PUMP
The charge pump current (ICP) is programmable to provide the
user with additional flexibility to optimize the PLL performance.
Table 8 lists the bit settings vs. the nominal charge pump
current.
Table 8. PLL Charge Pump Current
ICP (CFR3<21:19>)
Charge Pump Current, ICP (μA)
000
212
001
237
010
262
011
287
100
312
101
337
110
363
111
387
EXTERNAL PLL LOOP FILTER COMPONENTS
The PLL_LOOP_FILTER pin provides a connection interface to
attach the external loop filter components. The ability to use
custom loop filter components gives the user more flexibility to
optimize the PLL performance. The PLL and external loop filter
components are shown in Figure 52.
PFD
CP
PLL_LOOP_FILTER
VCO
÷N
PLL OUT
PLL IN
AVDD
REFCLK PLL
2
R1
C1
C2
06384-
030
Figure 52. REFCLK PLL External Loop Filter
In the prevailing literature, this configuration yields a third-
order, Type II PLL. To calculate the loop filter component
values, begin with the feedback divider value (N), the gain of
the phase detector (KD), and the gain of the VCO (KV) based on
loop filter component values depend on the desired open-loop
bandwidth (fOL) and phase margin (φ), as follows:
( )
+
=
φ
K
Nf
π
R1
V
D
OL
sin
1
(7)
( )
(
)2
2
tan
OL
V
D
f
N
K
C1
π
φ
=
(8)
( )
( )
=
φ
f
π
N
K
C2
OL
V
D
cos
sin
1
)
2
(
2
(9)
where:
KD equals the programmed value of ICP.
Ensure that proper units are used for the variables in Equation 7
through Equation 9. ICP must be in amps, not μA as appears in
loop bandwidth (fOL) must be in Hz; the phase margin (φ) must
be in radians.
For example, suppose the PLL is programmed such that
ICP = 287 μA, KV = 625 MHz/V, and N = 25. If the desired loop
bandwidth and phase margin are 50 kHz and 45°, respectively,
the loop filter component values are R1 = 52.85 , C1 = 145.4 nF,
and C2 = 30.11 nF.
PLL LOCK INDICATION
When the PLL is in use, the PLL_LOCK pin provides an active
high indication that the PLL has locked to the REFCLK input
signal. When the PLL is bypassed, the PLL_LOCK pin defaults
to Logic 0.
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| AD9957BSVZREEL13 | 制造商:AD 制造商全称:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
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| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
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