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参数资料
| 型号： | AD9957BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 34/64页 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1,000 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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AD9957
Data Sheet
Rev. C | Page 4 of 64
REVISION HISTORY
4/12—Rev. B to Rev. C
Changes to Table 1............................................................................ 7
Changes to Table 3.......................................................................... 11
Change to Sync Generator Section............................................... 41
Changes to Sync Receiver Section and Setup/Hold Validation
Section.............................................................................................. 42
Changes to Table 13........................................................................ 50
Changes to Table 19........................................................................ 57
Changes to Table 26........................................................................ 59
10/10—Rev. A to Rev. B
Changes to Data Rate in Features Section..................................... 1
Changes to Specifications Section.................................................. 6
Added EPAD Notation to Figure 4 and Table 3 ........................... 9
Changes to XTAL_SEL Pin Description...................................... 11
Changes to BlackFin Interface (BFI) Mode Section .................. 18
Changes to Figure 30 and Figure 31............................................. 22
Changes to Programmable Interpolating Filter Section............ 24
Changes to Fifth Paragraph of Quadrature Modulator Section......25
Changes to RAM Segment Registers Section ............................. 27
Changes to RAM Playback Operation Section........................... 28
Changes to Control Interface—Serial I/O Section..................... 47
Added to I/O_UPDATE, SYNC_CLK, and System Clock
Relationships Section and Figure 64 ............................................ 49
Changes to Default Values of Profile 0 Register—Single Tone
(0x0E) and Profile 0 Register—QDUC (0x0E) in Table 14....... 51
Changes to Default Values in Table 15......................................... 52
Changes to Default Values in Table 16......................................... 53
Changes to Default Values in Table 17......................................... 54
Updated Outline Dimensions ....................................................... 61
1/08—Rev. 0 to Rev. A
Changes to REFCLK Multiplier Specification...............................3
Changes to I/O_Update/Profile<2:0>/RT Timing
Characteristics and I/Q Input Timing Characteristics.................5
Replaced Pin Configuration and Function Descriptions
Section.................................................................................................8
Changes to Figure 25 Through Figure 29.................................... 15
Deleted Table 4, Renumbered Sequentially ................................ 20
Changes to DDS Core Section...................................................... 24
Changes to Figure 47 and Table 6................................................. 33
Replaced Synchronization of Multiple Devices Section............ 39
Added I/Q Path Latency Section.................................................. 44
Added Power Supply Partitioning Section.................................. 45
Changes to General Serial I/O Operation Section..................... 46
Changes to Table 13 ....................................................................... 48
Changes to Table 14 ....................................................................... 49
Changes to Table 19 ....................................................................... 54
Changes to Table 20 ....................................................................... 56
Changes to GPIO Configuration Register and
GPIO Data Register Sections ........................................................ 58
5/07—Revision 0: Initial Version
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