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参数资料
| 型号： | AD9957BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 55/64页 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1,000 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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Data Sheet
AD9957
Rev. C | Page 59 of 64
RAM Segment Register 1
Address 0x06, six bytes are assigned to this register. This register is only active if CFR1<31> = 1 and there is a Logic 1 to Logic 0 transition
on the RT pin.
Table 24. Bit Descriptions for RAM Segment Register 1
Bit(s)
Mnemonic
Description
47:32
RAM Address Step
Rate 1
This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM
address range.
31:22
RAM End Address 1
This 10-bit number identifies the ending address for the RAM state machine.
21:16
Open
15:6
RAM Start Address 1
This 10-bit number identifies the starting address for the RAM state machine.
5:3
Open
2:0
RAM Playback Mode 1
This 3-bit number identifies the playback mode for the RAM state machine (see Table 5).
Amplitude Scale Factor (ASF) Register
Address 0x09, four bytes are assigned to this register. This register is only active if CFR1<9> = 1.
Table 25. Bit Descriptions for ASF Register
Bit(s)
Mnemonic
Description
31:16
Amplitude Ramp Rate
Ineffective unless CFR1<8> = 1. This 16-bit number controls the rate at which the OSK controller
updates amplitude changes to the DDS.
15:2
Amplitude Scale Factor
If CFR1<8> = 0 and CFR1<23> = 0, then this 14-bit number is the amplitude scale factor for the DDS.
If CFR1<8> = 0 and CFR1<23> = 1, then this 14-bit number is the amplitude scale factor for the DDS
when the OSK pin is Logic 1.
If CFR1<8> = 1, then this 14-bit number sets a ceiling on the maximum allowable amplitude scale factor
for the DDS.
1:0
Amplitude Step Size
Ineffective unless CFR1<8> = 1. This 2-bit number controls the step size for amplitude changes to the
DDS (see Table 9).
Multichip Sync Register
Address 0x0A, four bytes are assigned to this register.
Table 26. Bit Descriptions for the Multichip Sync Register
Bit(s)
Mnemonic
Description
31:28
Sync Validation Delay
Default is 0000b. This 4-bit number sets the timing skew (in ~75 ps increments) between SYSCLK and
the delayed sync-in signal for the synchronization validation block in the synchronization receiver.
27
Sync Receiver Enable
0: synchronization clock receiver disabled (default).
1: synchronization clock receiver enabled.
26
Sync Generator Enable
0: synchronization clock generator disabled (default).
1: synchronization clock generator enabled.
25
Sync Generator Polarity
0: synchronization clock generator coincident with the rising edge of the system clock (default).
1: synchronization clock generator coincident with the falling edge of the system clock.
24
Open
23:18
Sync State Preset Value
Default is 000000b. This 6-bit number is the state that the internal clock generator assumes when it
receives a sync pulse.
17:16
Open
15:11
Sync Generator Delay
Default is 00000b. This 5-bit number sets the output delay (in ~75 ps increments) of the synchronization
generator.
10:8
Open
7:3
Sync Receiver Delay
Default is 00000b. This 5-bit number sets the delay input delay (in ~75 ps increments) of the
synchronization receiver.
2:0
Open
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| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
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