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| 型号： | AD9985BSTZ-110 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/32页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 8BIT 110MSPS 80LQFP |
| 标准包装： | 1 |
| 应用： | 视频 |
| 接口： | 串行 |
| 电源电压： | 2.2 V ~ 3.45 V |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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AD9985
Rev. 0 | Page 20 of 32
CLAMP TIMING
05
7–0
Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp.
When Clamp Function (Register 0FH, Bit 7) = 0, a
clamp signal is generated internally, at a position
established by the clamp placement and for a duration
set by the clamp duration. Clamping is started (Clamp
Placement) pixel periods after the trailing edge of
Hsync. The clamp placement may be programmed to
any value between 1 and 255.
The clamp should be placed during a time that the
input signal presents a stable black-level reference,
usually the back porch period between Hsync and the
image.
When Clamp Function = 1, this register is ignored.
06
7–0
Clamp Duration
An 8-bit register that sets the duration of the
internally generated clamp.
For the best results, the clamp duration should be set
to include the majority of the black reference signal
time that follows the Hsync signal trailing edge.
Insufficient clamping time can produce brightness
changes at the top of the screen, and a slow recovery
from large changes in the average picture level (APL),
or brightness.
When Clamp Function = 1, this register is ignored.
HSYNC PULSEWIDTH
07
7–0
Hsync Output Pulsewidth
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by
the internally generated, phase-adjusted PLL feedback
clock. The AD9985 then counts a number of pixel
clocks equal to the value in this register. This triggers
the trailing edge of the Hsync output, which is also
phase adjusted.
INPUT GAIN
08
7–0
Red Channel Gain Adjust
An 8-bit word that sets the gain of the Red channel.
The AD9985 can accommodate input signals with a
full-scale range of between 0.5 V and 1.0 V p-p.
Setting REDGAIN to 255 corresponds to a 1.0 V input
range. A REDGAIN of 0 establishes a 0.5 V input
range. Note that increasing REDGAIN results in the
picture having less contrast (the input signal uses
fewer of the available converter codes). See Figure 4.
09
7–0
Green Channel Gain Adjust
An 8-bit word that sets the gain of the Green channel.
See REDGAIN (08).
0A
7–0
Blue Channel Gain Adjust
An 8-bit word that sets the gain of the Blue channel.
See REDGAIN (08).
INPUT OFFSET
0B
7–1
Red Channel Offset Adjust
This and the following two offset registers have two
modes of operation. One mode is when the auto offset
function is turned off (manual mode) and the other is
when auto offset is turned on.
When in manual offset adjustment mode (auto offset
turned off) this register behaves exactly like the
AD9883A. It is a 7-bit offset binary word that sets the
dc offset of the Red channel. One LSB of offset
adjustment equals approximately one LSB change in
the ADC offset. Therefore, the absolute magnitude of
the offset adjustment scales as the gain of the channel
is changed. A nominal setting of 63 results in the
channel nominally clamping the back porch (during
the clamping interval) to Code 00. An offset setting of
127 results in the channel clamping to Code 64 of the
ADC. An offset setting of 0 clamps to Code –63 (off
the bottom of the range). Increasing the value of Red
Offset decreases the brightness of the channel.
When in auto offset mode, the value in this register is
digitally added to the red channel ADC output. The
purpose of doing this is to match a benefit that is
present with manual offset adjustment. Adjusting
these registers is an easy way to make brightness
adjustments. Although some signal range is lost with
this method, it has proven to be a very popular
function. In order to be able to increase and decrease
brightness, the values in these registers in this mode
are signed twos complement (as opposed to manual
mode where the values in this register are binary). The
digital adder is used only when in auto offset mode.
Although it cannot be disabled, setting this register to
all 0’s will effectively disable it by always adding 0.
0C
7–1
Green Channel Offset Adjust
This register works exactly like the Red Channel
Offset Adjust register (0Bh), except it is for the Green
Channel.
0D
7–1
Blue Channel Offset Adjust
This register works exactly like the Red Channel
Offset Adjust register (0Bh), except it is for the Blue
Channel.
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